The_Mission.mdwn

   1 > We believe a computer should be safe to use, and this starts with a
   2 > safe processor.
   3
   4 # The Mission
   5
   6 - to provide a libre, secure and transparently developed hybrid CPU VPU
   7   GPU architecture to the world.
   8 - to maximize the degree of trust a customer or user can place in
   9   products using our processor designs.
  10 - through significantly reduced product development costs and time to
  11   market, incentivise mass volume appliance manufacturers to ensure
  12   that end-users of their products enjoy the same level of access to
  13   full Board Support Package source code and Reference Designs that
  14   they have, including for the processor hardware design.
  15 - to disincentivise Tivoisation, the deployment of DRM and other lockout
  16   techniques that interfere with end-user trust in the products that
  17   they legitimately own.
  18
  19 To accomplish this we:
  20
  21 - use collaborative techniques
  22 - operate entirely transparently
  23 - invite developers and experts around the world to contribute without NDAs
  24 - invite inventors to contribute relevant patents to patent pools (OIN)
  25
  26 # The Means:
  27
  28 - provide the customer the **freedom to study, modify, and redistribute**
  29   the full SoC source from HDL and boot loader to down to the VLSI.
  30 - engage in **full transparency** at every level of the development,
  31   right from the inception through to delivery of silicon.  no exceptions.
  32 - listen to **constructive input** from world-leading industry experts,
  33   engineers and enthusiasts alike, in real-time, without NDAs creating
  34   artificial barriers to communication and hampering success.
  35
  36 # The Market:
  37
  38  - chromebooks
  39  - smartphones
  40  - tablets
  41  - industrial boards
  42  - single-board computers (like the Raspberry Pi)
  43  - wearables
  44  - CV capable flight controller for lightweight drones
  45  - whatever you want
  46
  47 # The Machines:
  48
  49 - our first target (Oct 2020): a single-core dual-issue 180nm 64-bit
  50   "demo" QFP chip that will also be a saleable product in the "Embedded"
  51   space (Arduino, STM32F, Ingenic jz4720).
  52 - a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU /
  53   GPU / VPU [and later an ML inference core], comparable to the Allwinner
  54   64 in capability.
  55 - Products based on customer - and client - driven needs and requirements
  56