cole.mdwn

   1 # Cole Poirier
   2
   3 Apprentice and assistant Project coordinator for Libre-SOC
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
   6
   7 # Status tracking
   8
   9 move things along from one stage to the next
  10
  11 ## Currently working on
  12
  13 - Reach out to lu_zero of Gentoo about SV POWER binutils
  14 - <https://bugs.libre-soc.org/show_bug.cgi?id=383> Complete first functional POWER9 Core
  15 - <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page
  16 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  17   - shared with lkcl
  18 - <https://bugs.libre-soc.org/show_bug.cgi?id=484> Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
  19   - shared with lkcl
  20 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> Create I-Cache from microwatt icache.vhdl
  21   - shared with lkcl
  22 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
  23   - shared with lkcl
  24 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
  25   - shared with lkcl
  26 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
  27 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
  28 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
  29 - <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial
  30 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG
  31 - <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
  32 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
  33
  34 ## List of things that need more fleshed out bug reports:
  35
  36 - Scoreboard documentation
  37   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
  38
  39
  40 - LDST documentation
  41   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
  42
  43
  44 ## Completed but not yet submitted
  45
  46 ## Submitted for NLNet RFP
  47
  48 submitted but not confirmed paid:
  49
  50 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
  51   - EUR 150
  52
  53 - Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
  54   - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
  55   - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
  56   - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
  57
  58 - <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
  59   - EUR 100
  60
  61 - <https://bugs.libre-soc.org/show_bug.cgi?id=472> Tutorial and dev page needed for mesa driver
  62   - EUR 100
  63
  64 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe discussion
  65   - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100)
  66
  67 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
  68   - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
  69
  70 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
  71
  72 ## Paid