cole.mdwn

   1 # Cole Poirier
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   3 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
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   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=325>
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   7 List of things that need more fleshed out bug reports:
   8
   9 * Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG
  10 * Bperm tutorial
  11 * Bugseverywhere
  12 * Competition to LS: Skywater 130nm production-ready PDK gets opensourced (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html)
  13 * Memory bus/L1/L2 Cache documentation  (bug #397)
  14 * Scoreboard documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
  15 * LDST documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
  16 * Follow up with graphics engineers, esp ones Yehowshua has already reached out to (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html)