cole.mdwn

   1 # Cole Poirier
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   3 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
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   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=325>
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   7 * Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401> (see also [Bug #397](https://bugs.libre-soc.org/show_bug.cgi?id=397))
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   9 List of things that need more fleshed out bug reports:
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  12 * Memory bus/L1/L2 Cache documentation <https://bugs.libre-soc.org/show_bug.cgi?id=397>
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  14 * Bperm tutorial
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  16 * Bugseverywhere, need specific bug report for discussing new bug tracker and migration (or also <https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go>)
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  18 * Competition to LS: Skywater 130nm production-ready PDK gets opensourced (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html>)
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  20 * Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
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  22 * LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
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  24 * Follow up with graphics engineers, esp ones Yehowshua has already reached out to (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html>)