cole.mdwn

   1 # Cole Poirier
   2
   3 Apprentice and assistant Project coordinator for Libre-SOC
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
   6
   7 # Status tracking
   8
   9 move things along from one stage to the next
  10
  11 ## Currently working on
  12
  13 - Recruiting more engineers to the project <https://bugs.libre-soc.org/show_bug.cgi?id=375> <https://bugs.libre-soc.org/show_bug.cgi?id=380> and make wiki pages(s) for this purpose <https://bugs.libre-soc.org/show_bug.cgi?id=379>
  14
  15 - Bperm tutorial <https://bugs.libre-soc.org/show_bug.cgi?id=388>
  16
  17 - Create a bug report for each diagram to be converted to SVG <https://bugs.libre-soc.org/show_bug.cgi?id=389>
  18
  19 - Reach out to developers of 'BlackParrot' RV64GC Multicore SoC <https://bugs.libre-soc.org/show_bug.cgi?id=394>
  20
  21 - Convert comp_unit_req_rel diagram to SVG <https://bugs.libre-soc.org/show_bug.cgi?id=442>
  22
  23 ## List of things that need more fleshed out bug reports:
  24
  25 * Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
  26
  27 * LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
  28
  29 ## Completed but not yet submitted
  30
  31 - Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401>
  32
  33 - Coriolis2 documentation and setup scripts
  34   <https://bugs.libre-soc.org/show_bug.cgi?id=291>
  35   <https://bugs.libre-soc.org/show_bug.cgi?id=178>
  36   <https://bugs.libre-soc.org/show_bug.cgi?id=320>
  37   <https://bugs.libre-soc.org/show_bug.cgi?id=404>
  38   <https://bugs.libre-soc.org/show_bug.cgi?id=138>
  39
  40 ## Submitted for NLNet RFP
  41
  42 submitted but not confirmed paid:
  43
  44 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
  45
  46 ## Paid