common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  17     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  18     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  19     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  20     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  21     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  22     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  23     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  24     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  25
  26     -- SPR numbers
  27     subtype spr_num_t is integer range 0 to 1023;
  28
  29     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  30
  31     constant SPR_XER    : spr_num_t := 1;
  32     constant SPR_LR     : spr_num_t := 8;
  33     constant SPR_CTR    : spr_num_t := 9;
  34     constant SPR_TAR    : spr_num_t := 815;
  35     constant SPR_DSISR  : spr_num_t := 18;
  36     constant SPR_DAR    : spr_num_t := 19;
  37     constant SPR_TB     : spr_num_t := 268;
  38     constant SPR_TBU    : spr_num_t := 269;
  39     constant SPR_DEC    : spr_num_t := 22;
  40     constant SPR_SRR0   : spr_num_t := 26;
  41     constant SPR_SRR1   : spr_num_t := 27;
  42     constant SPR_CFAR   : spr_num_t := 28;
  43     constant SPR_HSRR0  : spr_num_t := 314;
  44     constant SPR_HSRR1  : spr_num_t := 315;
  45     constant SPR_SPRG0  : spr_num_t := 272;
  46     constant SPR_SPRG1  : spr_num_t := 273;
  47     constant SPR_SPRG2  : spr_num_t := 274;
  48     constant SPR_SPRG3  : spr_num_t := 275;
  49     constant SPR_SPRG3U : spr_num_t := 259;
  50     constant SPR_HSPRG0 : spr_num_t := 304;
  51     constant SPR_HSPRG1 : spr_num_t := 305;
  52     constant SPR_PID    : spr_num_t := 48;
  53     constant SPR_PRTBL  : spr_num_t := 720;
  54     constant SPR_PVR    : spr_num_t := 287;
  55
  56     -- GPR indices in the register file (GPR only)
  57     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  58
  59     -- Extended GPR index (can hold an SPR or a FPR)
  60     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  61
  62     -- FPR indices
  63     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  64
  65     -- Some SPRs are stored in the register file, they use the magic
  66     -- GPR numbers above 31.
  67     --
  68     -- The function fast_spr_num() returns the corresponding fast
  69     -- pseudo-GPR number for a given SPR number. The result MSB
  70     -- indicates if this is indeed a fast SPR. If clear, then
  71     -- the SPR is not stored in the GPR file.
  72     --
  73     -- FPRs are also stored in the register file, using GSPR
  74     -- numbers from 64 to 95.
  75     --
  76     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  77
  78     -- Indices conversion functions
  79     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  80     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  81     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  82     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  83     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
  84
  85     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  86     -- in the CR file as a kind of CR extension (with a separate write
  87     -- control). The rest is stored as a fast SPR.
  88     type xer_common_t is record
  89         ca : std_ulogic;
  90         ca32 : std_ulogic;
  91         ov : std_ulogic;
  92         ov32 : std_ulogic;
  93         so : std_ulogic;
  94     end record;
  95     constant xerc_init : xer_common_t := (others => '0');
  96
  97     -- FPSCR bit numbers
  98     constant FPSCR_FX     : integer := 63 - 32;
  99     constant FPSCR_FEX    : integer := 63 - 33;
 100     constant FPSCR_VX     : integer := 63 - 34;
 101     constant FPSCR_OX     : integer := 63 - 35;
 102     constant FPSCR_UX     : integer := 63 - 36;
 103     constant FPSCR_ZX     : integer := 63 - 37;
 104     constant FPSCR_XX     : integer := 63 - 38;
 105     constant FPSCR_VXSNAN : integer := 63 - 39;
 106     constant FPSCR_VXISI  : integer := 63 - 40;
 107     constant FPSCR_VXIDI  : integer := 63 - 41;
 108     constant FPSCR_VXZDZ  : integer := 63 - 42;
 109     constant FPSCR_VXIMZ  : integer := 63 - 43;
 110     constant FPSCR_VXVC   : integer := 63 - 44;
 111     constant FPSCR_FR     : integer := 63 - 45;
 112     constant FPSCR_FI     : integer := 63 - 46;
 113     constant FPSCR_C      : integer := 63 - 47;
 114     constant FPSCR_FL     : integer := 63 - 48;
 115     constant FPSCR_FG     : integer := 63 - 49;
 116     constant FPSCR_FE     : integer := 63 - 50;
 117     constant FPSCR_FU     : integer := 63 - 51;
 118     constant FPSCR_VXSOFT : integer := 63 - 53;
 119     constant FPSCR_VXSQRT : integer := 63 - 54;
 120     constant FPSCR_VXCVI  : integer := 63 - 55;
 121     constant FPSCR_VE     : integer := 63 - 56;
 122     constant FPSCR_OE     : integer := 63 - 57;
 123     constant FPSCR_UE     : integer := 63 - 58;
 124     constant FPSCR_ZE     : integer := 63 - 59;
 125     constant FPSCR_XE     : integer := 63 - 60;
 126     constant FPSCR_NI     : integer := 63 - 61;
 127     constant FPSCR_RN     : integer := 63 - 63;
 128
 129     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
 130
 131     -- For now, fixed 16 sources, make this either a parametric
 132     -- package of some sort or an unconstrainted array.
 133     type ics_to_icp_t is record
 134         -- Level interrupts only, ICS just keeps prsenting the
 135         -- highest priority interrupt. Once handling edge, something
 136         -- smarter involving handshake & reject support will be needed
 137         src : std_ulogic_vector(3 downto 0);
 138         pri : std_ulogic_vector(7 downto 0);
 139     end record;
 140
 141     -- This needs to die...
 142     type ctrl_t is record
 143         tb: std_ulogic_vector(63 downto 0);
 144         dec: std_ulogic_vector(63 downto 0);
 145         msr: std_ulogic_vector(63 downto 0);
 146         cfar: std_ulogic_vector(63 downto 0);
 147         irq_state : irq_state_t;
 148         srr1: std_ulogic_vector(63 downto 0);
 149     end record;
 150
 151     type Fetch1ToIcacheType is record
 152         req: std_ulogic;
 153         virt_mode : std_ulogic;
 154         priv_mode : std_ulogic;
 155         big_endian : std_ulogic;
 156         stop_mark: std_ulogic;
 157         sequential: std_ulogic;
 158         nia: std_ulogic_vector(63 downto 0);
 159     end record;
 160
 161     type IcacheToDecode1Type is record
 162         valid: std_ulogic;
 163         stop_mark: std_ulogic;
 164         fetch_failed: std_ulogic;
 165         nia: std_ulogic_vector(63 downto 0);
 166         insn: std_ulogic_vector(31 downto 0);
 167         big_endian: std_ulogic;
 168     end record;
 169
 170     type Decode1ToDecode2Type is record
 171         valid: std_ulogic;
 172         stop_mark : std_ulogic;
 173         nia: std_ulogic_vector(63 downto 0);
 174         insn: std_ulogic_vector(31 downto 0);
 175         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 176         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 177         decode: decode_rom_t;
 178         br_pred: std_ulogic; -- Branch was predicted to be taken
 179         big_endian: std_ulogic;
 180     end record;
 181     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 182         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 183          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init,
 184          br_pred => '0', big_endian => '0');
 185
 186     type Decode1ToFetch1Type is record
 187         redirect     : std_ulogic;
 188         redirect_nia : std_ulogic_vector(63 downto 0);
 189     end record;
 190
 191     type Decode2ToExecute1Type is record
 192         valid: std_ulogic;
 193         unit : unit_t;
 194         insn_type: insn_type_t;
 195         nia: std_ulogic_vector(63 downto 0);
 196         write_reg: gspr_index_t;
 197         read_reg1: gspr_index_t;
 198         read_reg2: gspr_index_t;
 199         read_data1: std_ulogic_vector(63 downto 0);
 200         read_data2: std_ulogic_vector(63 downto 0);
 201         read_data3: std_ulogic_vector(63 downto 0);
 202         bypass_data1: std_ulogic;
 203         bypass_data2: std_ulogic;
 204         bypass_data3: std_ulogic;
 205         cr: std_ulogic_vector(31 downto 0);
 206         bypass_cr : std_ulogic;
 207         xerc: xer_common_t;
 208         lr: std_ulogic;
 209         rc: std_ulogic;
 210         oe: std_ulogic;
 211         invert_a: std_ulogic;
 212         invert_out: std_ulogic;
 213         input_carry: carry_in_t;
 214         output_carry: std_ulogic;
 215         input_cr: std_ulogic;
 216         output_cr: std_ulogic;
 217         is_32bit: std_ulogic;
 218         is_signed: std_ulogic;
 219         insn: std_ulogic_vector(31 downto 0);
 220         data_len: std_ulogic_vector(3 downto 0);
 221         byte_reverse : std_ulogic;
 222         sign_extend : std_ulogic;                       -- do we need to sign extend?
 223         update : std_ulogic;                            -- is this an update instruction?
 224         reserve : std_ulogic;                           -- set for larx/stcx
 225         br_pred : std_ulogic;
 226         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 227         second : std_ulogic;                            -- set if this is the second op
 228     end record;
 229     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 230         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 231          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
 232          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 233          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 234          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 235          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 236          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 237          repeat => '0', second => '0', others => (others => '0'));
 238
 239     type MultiplyInputType is record
 240         valid: std_ulogic;
 241         data1: std_ulogic_vector(63 downto 0);
 242         data2: std_ulogic_vector(63 downto 0);
 243         addend: std_ulogic_vector(127 downto 0);
 244         is_32bit: std_ulogic;
 245         not_result: std_ulogic;
 246     end record;
 247     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 248                                                        is_32bit => '0', not_result => '0',
 249                                                        others => (others => '0'));
 250
 251     type MultiplyOutputType is record
 252         valid: std_ulogic;
 253         result: std_ulogic_vector(127 downto 0);
 254         overflow : std_ulogic;
 255     end record;
 256     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 257                                                          others => (others => '0'));
 258
 259     type Execute1ToDividerType is record
 260         valid: std_ulogic;
 261         dividend: std_ulogic_vector(63 downto 0);
 262         divisor: std_ulogic_vector(63 downto 0);
 263         is_signed: std_ulogic;
 264         is_32bit: std_ulogic;
 265         is_extended: std_ulogic;
 266         is_modulus: std_ulogic;
 267         neg_result: std_ulogic;
 268     end record;
 269     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 270                                                               is_extended => '0', is_modulus => '0',
 271                                                               neg_result => '0', others => (others => '0'));
 272
 273     type Decode2ToRegisterFileType is record
 274         read1_enable : std_ulogic;
 275         read1_reg : gspr_index_t;
 276         read2_enable : std_ulogic;
 277         read2_reg : gspr_index_t;
 278         read3_enable : std_ulogic;
 279         read3_reg : gspr_index_t;
 280     end record;
 281
 282     type RegisterFileToDecode2Type is record
 283         read1_data : std_ulogic_vector(63 downto 0);
 284         read2_data : std_ulogic_vector(63 downto 0);
 285         read3_data : std_ulogic_vector(63 downto 0);
 286     end record;
 287
 288     type Decode2ToCrFileType is record
 289         read : std_ulogic;
 290     end record;
 291
 292     type CrFileToDecode2Type is record
 293         read_cr_data   : std_ulogic_vector(31 downto 0);
 294         read_xerc_data : xer_common_t;
 295     end record;
 296
 297     type Execute1ToFetch1Type is record
 298         redirect: std_ulogic;
 299         virt_mode: std_ulogic;
 300         priv_mode: std_ulogic;
 301         big_endian: std_ulogic;
 302         mode_32bit: std_ulogic;
 303         redirect_nia: std_ulogic_vector(63 downto 0);
 304     end record;
 305     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 306                                                              priv_mode => '0', big_endian => '0',
 307                                                              mode_32bit => '0', others => (others => '0'));
 308
 309     type Execute1ToLoadstore1Type is record
 310         valid : std_ulogic;
 311         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 312         nia : std_ulogic_vector(63 downto 0);
 313         insn : std_ulogic_vector(31 downto 0);
 314         addr1 : std_ulogic_vector(63 downto 0);
 315         addr2 : std_ulogic_vector(63 downto 0);
 316         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 317         write_reg : gspr_index_t;
 318         length : std_ulogic_vector(3 downto 0);
 319         ci : std_ulogic;                                -- cache-inhibited load/store
 320         byte_reverse : std_ulogic;
 321         sign_extend : std_ulogic;                       -- do we need to sign extend?
 322         update : std_ulogic;                            -- is this an update instruction?
 323         update_reg : gpr_index_t;                       -- if so, the register to update
 324         xerc : xer_common_t;
 325         reserve : std_ulogic;                           -- set for larx/stcx.
 326         rc : std_ulogic;                                -- set for stcx.
 327         virt_mode : std_ulogic;                         -- do translation through TLB
 328         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 329         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 330         is_32bit : std_ulogic;
 331         repeat : std_ulogic;
 332         second : std_ulogic;
 333     end record;
 334     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 335                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 336                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 337                                                                      nia => (others => '0'), insn => (others => '0'),
 338                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 339                                                                      write_reg => (others => '0'), length => (others => '0'),
 340                                                                      mode_32bit => '0', is_32bit => '0',
 341                                                                      repeat => '0', second => '0', others => (others => '0'));
 342
 343     type Loadstore1ToExecute1Type is record
 344         busy : std_ulogic;
 345         exception : std_ulogic;
 346         alignment : std_ulogic;
 347         invalid : std_ulogic;
 348         perm_error : std_ulogic;
 349         rc_error : std_ulogic;
 350         badtree : std_ulogic;
 351         segment_fault : std_ulogic;
 352         instr_fault : std_ulogic;
 353     end record;
 354
 355     type Loadstore1ToDcacheType is record
 356         valid : std_ulogic;
 357         load : std_ulogic;                              -- is this a load
 358         dcbz : std_ulogic;
 359         nc : std_ulogic;
 360         reserve : std_ulogic;
 361         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 362         atomic_last : std_ulogic;
 363         virt_mode : std_ulogic;
 364         priv_mode : std_ulogic;
 365         addr : std_ulogic_vector(63 downto 0);
 366         data : std_ulogic_vector(63 downto 0);
 367         byte_sel : std_ulogic_vector(7 downto 0);
 368     end record;
 369
 370     type DcacheToLoadstore1Type is record
 371         valid : std_ulogic;
 372         data : std_ulogic_vector(63 downto 0);
 373         store_done : std_ulogic;
 374         error : std_ulogic;
 375         cache_paradox : std_ulogic;
 376     end record;
 377
 378     type Loadstore1ToMmuType is record
 379         valid : std_ulogic;
 380         tlbie : std_ulogic;
 381         slbia : std_ulogic;
 382         mtspr : std_ulogic;
 383         iside : std_ulogic;
 384         load  : std_ulogic;
 385         priv  : std_ulogic;
 386         sprn  : std_ulogic_vector(9 downto 0);
 387         addr  : std_ulogic_vector(63 downto 0);
 388         rs    : std_ulogic_vector(63 downto 0);
 389     end record;
 390
 391     type MmuToLoadstore1Type is record
 392         done       : std_ulogic;
 393         err        : std_ulogic;
 394         invalid    : std_ulogic;
 395         badtree    : std_ulogic;
 396         segerr     : std_ulogic;
 397         perm_error : std_ulogic;
 398         rc_error   : std_ulogic;
 399         sprval     : std_ulogic_vector(63 downto 0);
 400     end record;
 401
 402     type MmuToDcacheType is record
 403         valid : std_ulogic;
 404         tlbie : std_ulogic;
 405         doall : std_ulogic;
 406         tlbld : std_ulogic;
 407         addr  : std_ulogic_vector(63 downto 0);
 408         pte   : std_ulogic_vector(63 downto 0);
 409     end record;
 410
 411     type DcacheToMmuType is record
 412         stall : std_ulogic;
 413         done  : std_ulogic;
 414         err   : std_ulogic;
 415         data  : std_ulogic_vector(63 downto 0);
 416     end record;
 417
 418     type MmuToIcacheType is record
 419         tlbld : std_ulogic;
 420         tlbie : std_ulogic;
 421         doall : std_ulogic;
 422         addr  : std_ulogic_vector(63 downto 0);
 423         pte   : std_ulogic_vector(63 downto 0);
 424     end record;
 425
 426     type Loadstore1ToWritebackType is record
 427         valid : std_ulogic;
 428         write_enable: std_ulogic;
 429         write_reg : gspr_index_t;
 430         write_data : std_ulogic_vector(63 downto 0);
 431         xerc : xer_common_t;
 432         rc : std_ulogic;
 433         store_done : std_ulogic;
 434     end record;
 435     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 436                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 437
 438     type Execute1ToWritebackType is record
 439         valid: std_ulogic;
 440         rc : std_ulogic;
 441         mode_32bit : std_ulogic;
 442         write_enable : std_ulogic;
 443         write_reg: gspr_index_t;
 444         write_data: std_ulogic_vector(63 downto 0);
 445         write_cr_enable : std_ulogic;
 446         write_cr_mask : std_ulogic_vector(7 downto 0);
 447         write_cr_data : std_ulogic_vector(31 downto 0);
 448         write_xerc_enable : std_ulogic;
 449         xerc : xer_common_t;
 450         exc_write_enable : std_ulogic;
 451         exc_write_reg : gspr_index_t;
 452         exc_write_data : std_ulogic_vector(63 downto 0);
 453     end record;
 454     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
 455                                                                    write_cr_enable => '0', exc_write_enable => '0',
 456                                                                    write_xerc_enable => '0', xerc => xerc_init,
 457                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 458                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 459                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 460
 461     type Execute1ToFPUType is record
 462         valid   : std_ulogic;
 463         op      : insn_type_t;
 464         nia     : std_ulogic_vector(63 downto 0);
 465         insn    : std_ulogic_vector(31 downto 0);
 466         single  : std_ulogic;
 467         fe_mode : std_ulogic_vector(1 downto 0);
 468         fra     : std_ulogic_vector(63 downto 0);
 469         frb     : std_ulogic_vector(63 downto 0);
 470         frc     : std_ulogic_vector(63 downto 0);
 471         frt     : gspr_index_t;
 472         rc      : std_ulogic;
 473         out_cr  : std_ulogic;
 474     end record;
 475     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 476                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 477                                                        fra => (others => '0'), frb => (others => '0'),
 478                                                        frc => (others => '0'), frt => (others => '0'),
 479                                                        single => '0', out_cr => '0');
 480
 481     type FPUToExecute1Type is record
 482         busy      : std_ulogic;
 483         exception : std_ulogic;
 484         interrupt : std_ulogic;
 485         illegal   : std_ulogic;
 486     end record;
 487     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 488
 489     type FPUToWritebackType is record
 490         valid           : std_ulogic;
 491         write_enable    : std_ulogic;
 492         write_reg       : gspr_index_t;
 493         write_data      : std_ulogic_vector(63 downto 0);
 494         write_cr_enable : std_ulogic;
 495         write_cr_mask   : std_ulogic_vector(7 downto 0);
 496         write_cr_data   : std_ulogic_vector(31 downto 0);
 497     end record;
 498     constant FPUToWritebackInit : FPUToWritebackType :=  (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 499
 500     type DividerToExecute1Type is record
 501         valid: std_ulogic;
 502         write_reg_data: std_ulogic_vector(63 downto 0);
 503         overflow : std_ulogic;
 504     end record;
 505     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 506                                                                others => (others => '0'));
 507
 508     type WritebackToRegisterFileType is record
 509         write_reg : gspr_index_t;
 510         write_data : std_ulogic_vector(63 downto 0);
 511         write_enable : std_ulogic;
 512     end record;
 513     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 514
 515     type WritebackToCrFileType is record
 516         write_cr_enable : std_ulogic;
 517         write_cr_mask : std_ulogic_vector(7 downto 0);
 518         write_cr_data : std_ulogic_vector(31 downto 0);
 519         write_xerc_enable : std_ulogic;
 520         write_xerc_data : xer_common_t;
 521     end record;
 522     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 523                                                                write_xerc_data => xerc_init,
 524                                                                write_cr_mask => (others => '0'),
 525                                                                write_cr_data => (others => '0'));
 526
 527 end common;
 528
 529 package body common is
 530     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 531     begin
 532         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 533     end;
 534     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 535        variable n : integer range 0 to 31;
 536        -- tmp variable introduced as workaround for VCS compilation
 537        -- simulation was failing with subtype constraint mismatch error
 538        -- see GitHub PR #173
 539        variable tmp : std_ulogic_vector(4 downto 0);
 540     begin
 541        case spr is
 542        when SPR_LR =>
 543            n := 0;
 544        when SPR_CTR =>
 545            n:= 1;
 546        when SPR_SRR0 =>
 547            n := 2;
 548        when SPR_SRR1 =>
 549            n := 3;
 550        when SPR_HSRR0 =>
 551            n := 4;
 552        when SPR_HSRR1 =>
 553            n := 5;
 554        when SPR_SPRG0 =>
 555            n := 6;
 556        when SPR_SPRG1 =>
 557            n := 7;
 558        when SPR_SPRG2 =>
 559            n := 8;
 560        when SPR_SPRG3 | SPR_SPRG3U =>
 561            n := 9;
 562        when SPR_HSPRG0 =>
 563            n := 10;
 564        when SPR_HSPRG1 =>
 565            n := 11;
 566        when SPR_XER =>
 567            n := 12;
 568        when SPR_TAR =>
 569            n := 13;
 570        when others =>
 571            n := 0;
 572            return "0000000";
 573        end case;
 574        tmp := std_ulogic_vector(to_unsigned(n, 5));
 575        return "01" & tmp;
 576     end;
 577
 578     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 579     begin
 580         return i(4 downto 0);
 581     end;
 582
 583     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 584     begin
 585         return "00" & i;
 586     end;
 587
 588     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 589     begin
 590         if s(5) = '1' then
 591             return s;
 592         else
 593             return gpr_to_gspr(g);
 594         end if;
 595     end;
 596
 597     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 598     begin
 599         return s(5);
 600     end;
 601
 602     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 603     begin
 604         return "10" & f;
 605     end;
 606 end common;