1 % Copyright 2024 Jacob Lifshay
4 \usepackage{beamerthemesplit
}
6 \usepackage[english
]{babel
}
9 \title[Fast Big-Integer Arithmetic on SVP64 ...
]{
10 Fast Big-Integer Arithmetic on SVP64 at up to
256-bits/cycle and beyond
13 \author{Jacob R. Lifshay
}
17 \logo{\includegraphics[height=
0.5cm
]{../../../images/lsoclogo.png
}}
25 \begin{frame
}[fragile
]
26 \frametitle{What is SVP64?
}
28 \item Vectorization Extension for PowerISA developed by
\href{https://libre-soc.org
}{Libre-SOC
}
30 \item Basically, a way to modify nearly any PowerISA instruction to run it in a HW loop.
35 setvl
0,
0,
3,
0,
1,
1 # makes stuff run
3 times
36 sv.add *r3, *r15, r12 # adds
3 times
39 add r3, r15, r12
\only<+(
1)->
{# no * means r12 doesn't increment
}
40 add r4, r16, r12
\only<+(
1)->
{# * means r3 and r15 increment
}
46 \begin{frame
}[fragile
]
47 \frametitle{Big-Integer Addition on SVP64
}
48 How can we use SVP64 to add
256-bit integers?
51 setvl
0,
0,
4,
0,
1,
1 # makes stuff run
4 times
52 addic
0,
0,
0 # clear CA (carry flag)
53 sv.adde *r4, *r4, *r8 # carry-propagating add
56 addic
0,
0,
0 # clear CA (carry flag)
65 \frametitle{Big-Integer Addition on an example CPU
}
67 SVP64 is designed for everything from tiny to big and fast CPUs, this example only shows a hypothetical big and fast CPU design
71 \frametitle{Big-Integer Addition on an example CPU
}
72 \input{bigint-add-pipe.dia-tex
}