conferences/ics2021.mdwn

   1 # ICS2021
   2
   3 14 June 2021
   4
   5 * <https://ics21.github.io/>
   6 * <https://www.timeanddate.com/worldclock/meetingtime.html?day=14&month=6&year=2021&p1=%20141&p2=236&p3=1234&p4=250&p5=24&p6=224&iv=0>
   7 * <https://meep-project.eu/events/ics-2021>
   8 * <https://www.youtube.com/channel/UCmkFegzIFCU-q33B7DAKfFQ>
   9 * <https://www.youtube.com/watch?v=LOCPTh4gVyc&t=3650s>
  10
  11 # Luke Leighton bio
  12
  13 Luke Kenneth Casson Leighton specialises in Libre Ethical Technology.
  14 He has been using, programming and reverse-engineering computing
  15 devices continuously for 44 years, has a BEng (Hons), ACGI, in
  16 Theory of Computing from Imperial College, and recently put that
  17 education to good use in the form of the Libre-SOC
  18 Project: an entirely Libre-Licensed 3D Hybrid CPU-VPU-GPU based on
  19 OpenPOWER. He writes poetry and has been developing a HEP Physics theory
  20 for the past 36 years in his spare time.
  21
  22 ## SVP64 Abstract
  23
  24 The OpenPOWER ISA has a strong multi-decades pedigree in Supercomputing:
  25 Matrix Multiply, 128-bit SIMD, BCD, Decimal Floating-point have been part
  26 of the ISA for decades, supporting Business and Scientific Computing.
  27 What the OpenPOWER ISA does not have is Vector processing, first
  28 successfully found in the Cray-1 Supercomputer, from 1976.
  29
  30 SVP64 is an initiative being developed by the Libre-SOC team and
  31 funded by NLnet, that brings Cray-style Variable-length Vectorisation
  32 to the OpenPOWER ISA in a seamless and non-disruptive fashion.  The team
  33 is keeping the OpenPOWER Foundation appraised of progress, and plans to
  34 submit SVP64 as an RFC to the newly-formed OpenPOWER ISA Working Group.
  35
  36 SVP64 is based on the concept of embedding scalar operations into
  37 a Vectorisation Context: effectively a simple Sub-Program-Counter for-loop.
  38 However that Vectorisation Context effectively extends each of the 200+
  39 primary scalar operations in the OpenPOWER ISA by a factor of 4,000,
  40 to produce a staggering and unprecedented 800,000 unique Vector opcodes.
  41
  42 Although SVP64 borrows from innovations in Computer Science over the
  43 past 50 years, including the original Cray Vectors, VLIW, Zero-overhead
  44 Loops from DSPs and Intel MMX, the end result is something entirely new.
  45 This talk will go through the development process of SVP64 and explain
  46 some of the innovative Vectorisation concepts that have never been seen
  47 before in any commercial or academic Vector ISA, including
  48 Twin-Predication and Condition Register "Post-result" predication,
  49 and how these will benefit Supercomputing performance and decrease
  50 power consumption, most notably by reducing program size and
  51 thus I-Cache usage whilst still maintaining high data throughput.
  52
  53 ## Comprehensive life-cycle of mixed testing: HDL to gates
  54
  55 The Libre-SOC Project is developed by Software Engineers with a Hardware
  56 background: in particular, Software Engineers with decades of experience
  57 in the Libre / Open software ecosystem.  There is a huge difference.
  58
  59 Software Engineers have it drummed into them from either training or
  60 bitter experience that unit tests are critical at every level.  Whilst
  61 the Validation Process for an ASIC goes through a rigorous process
  62 in the Synthesis Tools to ensure its correctness at every step, the
  63 actual HDL itself, shockingly, is typically put together in its entirety.
  64 Only on completion are high-level (binary) unit tests run.  Errors
  65 in a low-level subsystem thus become extremely hard to find.
  66
  67 In addition to that, as a Libre Project, we have had to use Libre
  68 VLSI tools. These are in active development and have not - yet -
  69 been used to develop ASICs beyond 130nm or over 1,000,000 gates.
  70 Our ASIC toolchain and HDL verification procedures are therefore
  71 functional but a little different from Industry-standard (proprietary)
  72 norm.
  73
  74 This talk will therefore show, by example, how we went from low-level
  75 modules (with unit tests and Formal Correctness Proofs), to pipelines
  76 (with unit tests and Formal Correctness Proofs), to a functional Core
  77 (with several thousand unit tests), right the way to ASIC layout,
  78 from which the Netlist was extracted and then co-simulated with cocotb.
  79 At each and every stage - both pre and post layout and on FPGA - it
  80 has been possible to run the exact same JTAG Boundary Scan and basic
  81 startup procedure.
  82
  83
  84 # Jean-Paul Chaput bio
  85
  86 Jean-Paul  Chaput  holds  a  Master Degree  in  MicroElectronics  and  Software
  87 Engineering.  He  joined the LIP6  laboratory within Sorbonne Université  or SU
  88 (formerly UPMC) in 2000.  Currently he is a Research Engineer in the Analog and
  89 Mixed  Signal  Team at  LIP6.   His  main focus  is  on  physical level  design
  90 software.   He  is  a  key   contributor  in  developing  and  maintaining  the
  91 Alliance/Coriolis VLSI  CAD projects for  CMOS technologies.  In  particular he
  92 contributed in developing  the routers of both Alliance/Coriolis  and the whole
  93 Coriolis toolchain infrastructure.   He his now a key  contributor in extending
  94 Alliance/Coriolis to  the Analog  Mixed-Signal integration for  nanometric CMOS
  95 technologies.
  96
  97 ## How to make an ASIC
  98
  99 * <https://youtu.be/EkCD6srelYo?t=99>
 100
 101 ## ICS 2021 Abstract
 102
 103 Starting in 1990, Sorbonne Université-CNRS/LIP6 developed Alliance, a complete
 104 VLSI CAD  toolchain released under GPL.   In this spirit, we  are assembling an
 105 upgraded  design flow  for ASICs  based on  FOSS tools  like GHDL  & Yosys  for
 106 logical synthesis and  Coriolis2 for physical design. We will  present the flow
 107 with a  focus on  the Coriolis2  part and the  LibreSOC first  prototype.  This
 108 should  be an  important  milestone toward  the creation  of  an open  hardware
 109 community.