crypto_router_asic.mdwn

   1 # Crypto-router ASIC
   2
   3 * NLnet page: [[nlnet_2021_crypto_router]]
   4 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
   5
   6 # Specifications
   7
   8 All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
   9
  10 * 300 mhz single-core,
  11   [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
  12   OpenPOWER CPU with
  13   [[openpower/sv/bitmanip]] extensions
  14 * 180/130 nm (TBD)
  15 * 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
  16   [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
  17    on-chip, built-in.
  18 * 2x USB [[shakti/m_class/ULPI]] PHYs
  19 * Direct DMA interface (independent bulk transfer)
  20 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
  21   GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
  22 * On-board Dual-ported SRAM (for Packet Buffers)
  23 * Opencores [[shakti/m_class/sdram]]
  24 * Wishbone interfaces to all peripherals
  25 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
  26   Interrupt Controller
  27
  28
  29
  30 # Example packet transfer
  31
  32 * Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
  33 * Packet is **directly** stored in internal (dual-ported SRAM) by
  34   the RGMII PHY itself
  35 * Interrupt notification is sent to the processor (XICS)
  36 * Processor inspects packet over Wishbone interface directly
  37   connected to 2nd SRAM port.
  38 * Processor computes, based on decoding the ETH Frame, where the
  39   packet must be sent to (which other RGM-II port: e.g. Port 2)
  40 * Processor initiates Memory-to-Memory DMA transfer
  41 * DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
  42   from one on-board SRAM to the target on-board SRAM associated with Port 2.
  43 * DMA Engine generates interrupt (XICS) to the CPU to say it is completed
  44 * Processor notifies target RGM-II PHY to activate "send" of frame out
  45   through target RGM-II port 2.
  46
  47 # Testing and Verification
  48
  49 We will need full HDL simulations as well as post P&R simulations.
  50 These may be achieved as follows:
  51
  52 * ISA-level unit tests as well as Formal Correctness Proofs.
  53   Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
  54   and individual unit tests for the
  55   [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
  56 * [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
  57   with some peripherals developed in c++ as verilator modules
  58 * nmigen-based OpenPOWER Libre-SOC core co-simulation such as
  59   this unit test,
  60   [test_issuer.py](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD)
  61 * [cocotb pre/post PnR](https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD) including GHDL, Icarus and Verilator
  62   (where best suited)
  63
  64 Actual instructions being developed (bitmanip) may therefore be
  65 unit tested prior to deployment.  Following that, rapid simulations
  66 may be achieved by running Litex (the same HDL may also easily
  67 be uploaded to an FPGA).  When it comes to Place-and-Route of the
  68 ASIC, the cocotb simulations may be used to verify that the GDS-II
  69 layout has not been "damaged" by the PnR tools.
  70
  71 Peripherals functionality tests must also be part of the simulations,
  72 particularly using cocotb, to ensure that they remain functional after PnR.
  73 Supercomputer access for compilation of verilator and/or cxxrtl is available
  74 through [[fed4fire]]
  75