execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40         bypass_data : out bypass_data_t;
  41         bypass_cr_data : out cr_bypass_data_t;
  42
  43         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  44
  45         icache_inval : out std_ulogic;
  46         terminate_out : out std_ulogic;
  47
  48         log_out : out std_ulogic_vector(14 downto 0);
  49         log_rd_addr : out std_ulogic_vector(31 downto 0);
  50         log_rd_data : in std_ulogic_vector(63 downto 0);
  51         log_wr_addr : in std_ulogic_vector(31 downto 0)
  52         );
  53 end entity execute1;
  54
  55 architecture behaviour of execute1 is
  56     type reg_type is record
  57         e : Execute1ToWritebackType;
  58         cur_instr : Decode2ToExecute1Type;
  59         busy: std_ulogic;
  60         terminate: std_ulogic;
  61         fp_exception_next : std_ulogic;
  62         trace_next : std_ulogic;
  63         prev_op : insn_type_t;
  64         next_lr : std_ulogic_vector(63 downto 0);
  65         br_taken : std_ulogic;
  66         mul_in_progress : std_ulogic;
  67         mul_finish : std_ulogic;
  68         div_in_progress : std_ulogic;
  69         cntz_in_progress : std_ulogic;
  70         last_nia : std_ulogic_vector(63 downto 0);
  71         redirect : std_ulogic;
  72         abs_br : std_ulogic;
  73         taken_br : std_ulogic;
  74         br_last : std_ulogic;
  75         do_intr : std_ulogic;
  76         vector : integer range 0 to 16#fff#;
  77         br_offset : std_ulogic_vector(63 downto 0);
  78         redir_mode : std_ulogic_vector(3 downto 0);
  79         log_addr_spr : std_ulogic_vector(31 downto 0);
  80     end record;
  81     constant reg_type_init : reg_type :=
  82         (e => Execute1ToWritebackInit,
  83          cur_instr => Decode2ToExecute1Init,
  84          busy => '0', terminate => '0',
  85          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL, br_taken => '0',
  86          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  87          next_lr => (others => '0'), last_nia => (others => '0'),
  88          redirect => '0', abs_br => '0', taken_br => '0', br_last => '0', do_intr => '0', vector => 0,
  89          br_offset => (others => '0'), redir_mode => "0000",
  90          others => (others => '0'));
  91
  92     signal r, rin : reg_type;
  93
  94     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  95     signal cr_in : std_ulogic_vector(31 downto 0);
  96
  97     signal valid_in : std_ulogic;
  98     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  99     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
 100     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
 101     signal rot_sign_ext: std_ulogic;
 102     signal rotator_result: std_ulogic_vector(63 downto 0);
 103     signal rotator_carry: std_ulogic;
 104     signal logical_result: std_ulogic_vector(63 downto 0);
 105     signal countzero_result: std_ulogic_vector(63 downto 0);
 106     signal alu_result: std_ulogic_vector(63 downto 0);
 107     signal adder_result: std_ulogic_vector(63 downto 0);
 108     signal misc_result: std_ulogic_vector(63 downto 0);
 109     signal muldiv_result: std_ulogic_vector(63 downto 0);
 110     signal spr_result: std_ulogic_vector(63 downto 0);
 111     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 112     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 113     signal next_nia : std_ulogic_vector(63 downto 0);
 114     signal current: Decode2ToExecute1Type;
 115
 116     -- multiply signals
 117     signal x_to_multiply: MultiplyInputType;
 118     signal multiply_to_x: MultiplyOutputType;
 119
 120     -- divider signals
 121     signal x_to_divider: Execute1ToDividerType;
 122     signal divider_to_x: DividerToExecute1Type;
 123
 124     -- random number generator signals
 125     signal random_raw  : std_ulogic_vector(63 downto 0);
 126     signal random_cond : std_ulogic_vector(63 downto 0);
 127     signal random_err  : std_ulogic;
 128
 129     -- signals for logging
 130     signal exception_log : std_ulogic;
 131     signal irq_valid_log : std_ulogic;
 132
 133     type privilege_level is (USER, SUPER);
 134     type op_privilege_array is array(insn_type_t) of privilege_level;
 135     constant op_privilege: op_privilege_array := (
 136         OP_ATTN => SUPER,
 137         OP_MFMSR => SUPER,
 138         OP_MTMSRD => SUPER,
 139         OP_RFID => SUPER,
 140         OP_TLBIE => SUPER,
 141         others => USER
 142         );
 143
 144     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 145         return boolean is
 146     begin
 147         if op_privilege(op) = SUPER then
 148             return true;
 149         elsif op = OP_MFSPR or op = OP_MTSPR then
 150             return insn(20) = '1';
 151         else
 152             return false;
 153         end if;
 154     end;
 155
 156     procedure set_carry(e: inout Execute1ToWritebackType;
 157                         carry32 : in std_ulogic;
 158                         carry : in std_ulogic) is
 159     begin
 160         e.xerc.ca32 := carry32;
 161         e.xerc.ca := carry;
 162         e.write_xerc_enable := '1';
 163     end;
 164
 165     procedure set_ov(e: inout Execute1ToWritebackType;
 166                      ov   : in std_ulogic;
 167                      ov32 : in std_ulogic) is
 168     begin
 169         e.xerc.ov32 := ov32;
 170         e.xerc.ov := ov;
 171         if ov = '1' then
 172             e.xerc.so := '1';
 173         end if;
 174         e.write_xerc_enable := '1';
 175     end;
 176
 177     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 178                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 179     begin
 180         return (ca xor msb_r) and not (msb_a xor msb_b);
 181     end;
 182
 183     function decode_input_carry(ic : carry_in_t;
 184                                 xerc : xer_common_t) return std_ulogic is
 185     begin
 186         case ic is
 187         when ZERO =>
 188             return '0';
 189         when CA =>
 190             return xerc.ca;
 191         when OV =>
 192             return xerc.ov;
 193         when ONE =>
 194             return '1';
 195         end case;
 196     end;
 197
 198     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 199         return std_ulogic_vector is
 200         variable msr_out: std_ulogic_vector(63 downto 0);
 201     begin
 202         -- ISA says this:
 203         --  Defined MSR bits are classified as either full func-
 204         --  tion or partial function. Full function MSR bits are
 205         --  saved in SRR1 or HSRR1 when an interrupt other
 206         --  than a System Call Vectored interrupt occurs and
 207         --  restored by rfscv, rfid, or hrfid, while partial func-
 208         --  tion MSR bits are not saved or restored.
 209         --  Full function MSR bits lie in the range 0:32, 37:41, and
 210         --  48:63, and partial function MSR bits lie in the range
 211         --  33:36 and 42:47. (Note this is IBM bit numbering).
 212         msr_out := (others => '0');
 213         msr_out(63 downto 31) := msr(63 downto 31);
 214         msr_out(26 downto 22) := msr(26 downto 22);
 215         msr_out(15 downto 0)  := msr(15 downto 0);
 216         return msr_out;
 217     end;
 218
 219     -- Tell vivado to keep the hierarchy for the random module so that the
 220     -- net names in the xdc file match.
 221     attribute keep_hierarchy : string;
 222     attribute keep_hierarchy of random_0 : label is "yes";
 223
 224 begin
 225
 226     rotator_0: entity work.rotator
 227         port map (
 228             rs => c_in,
 229             ra => a_in,
 230             shift => b_in(6 downto 0),
 231             insn => e_in.insn,
 232             is_32bit => e_in.is_32bit,
 233             right_shift => right_shift,
 234             arith => e_in.is_signed,
 235             clear_left => rot_clear_left,
 236             clear_right => rot_clear_right,
 237             sign_ext_rs => rot_sign_ext,
 238             result => rotator_result,
 239             carry_out => rotator_carry
 240             );
 241
 242     logical_0: entity work.logical
 243         port map (
 244             rs => c_in,
 245             rb => b_in,
 246             op => e_in.insn_type,
 247             invert_in => e_in.invert_a,
 248             invert_out => e_in.invert_out,
 249             result => logical_result,
 250             datalen => e_in.data_len
 251             );
 252
 253     countzero_0: entity work.zero_counter
 254         port map (
 255             clk => clk,
 256             rs => c_in,
 257             count_right => e_in.insn(10),
 258             is_32bit => e_in.is_32bit,
 259             result => countzero_result
 260             );
 261
 262     multiply_0: entity work.multiply
 263         port map (
 264             clk => clk,
 265             m_in => x_to_multiply,
 266             m_out => multiply_to_x
 267             );
 268
 269     divider_0: entity work.divider
 270         port map (
 271             clk => clk,
 272             rst => rst,
 273             d_in => x_to_divider,
 274             d_out => divider_to_x
 275             );
 276
 277     random_0: entity work.random
 278         port map (
 279             clk => clk,
 280             data => random_cond,
 281             raw => random_raw,
 282             err => random_err
 283             );
 284
 285     dbg_msr_out <= ctrl.msr;
 286     log_rd_addr <= r.log_addr_spr;
 287
 288     a_in <= e_in.read_data1;
 289     b_in <= e_in.read_data2;
 290     c_in <= e_in.read_data3;
 291
 292     busy_out <= l_in.busy or r.busy or fp_in.busy;
 293     valid_in <= e_in.valid and not busy_out;
 294
 295     terminate_out <= r.terminate;
 296
 297     current <= e_in when r.busy = '0' else r.cur_instr;
 298
 299     -- Result mux
 300     with current.result_sel select alu_result <=
 301         adder_result       when "000",
 302         logical_result     when "001",
 303         rotator_result     when "010",
 304         muldiv_result      when "011",
 305         countzero_result   when "100",
 306         spr_result         when "101",
 307         next_nia           when "110",
 308         misc_result        when others;
 309
 310     execute1_0: process(clk)
 311     begin
 312         if rising_edge(clk) then
 313             if rst = '1' then
 314                 r <= reg_type_init;
 315                 ctrl.tb <= (others => '0');
 316                 ctrl.dec <= (others => '0');
 317                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 318                 ctrl.irq_state <= WRITE_SRR0;
 319             else
 320                 r <= rin;
 321                 ctrl <= ctrl_tmp;
 322                 if valid_in = '1' then
 323                     report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
 324                         " wr=" & to_hstring(rin.e.write_reg) & " we=" & std_ulogic'image(rin.e.write_enable) &
 325                         " tag=" & integer'image(rin.e.instr_tag.tag) & std_ulogic'image(rin.e.instr_tag.valid);
 326                 end if;
 327             end if;
 328         end if;
 329     end process;
 330
 331     execute1_1: process(all)
 332         variable v : reg_type;
 333         variable a_inv : std_ulogic_vector(63 downto 0);
 334         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 335         variable addg6s : std_ulogic_vector(63 downto 0);
 336         variable isel_result : std_ulogic_vector(63 downto 0);
 337         variable darn : std_ulogic_vector(63 downto 0);
 338         variable mfcr_result : std_ulogic_vector(63 downto 0);
 339         variable setb_result : std_ulogic_vector(63 downto 0);
 340         variable newcrf : std_ulogic_vector(3 downto 0);
 341         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 342         variable crnum : crnum_t;
 343         variable crbit : integer range 0 to 31;
 344         variable scrnum : crnum_t;
 345         variable lo, hi : integer;
 346         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 347         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 348         variable bo, bi : std_ulogic_vector(4 downto 0);
 349         variable bf, bfa : std_ulogic_vector(2 downto 0);
 350         variable cr_op : std_ulogic_vector(9 downto 0);
 351         variable cr_operands : std_ulogic_vector(1 downto 0);
 352         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 353         variable btnum, banum, bbnum : integer range 0 to 31;
 354         variable crresult : std_ulogic;
 355         variable l : std_ulogic;
 356         variable carry_32, carry_64 : std_ulogic;
 357         variable sign1, sign2 : std_ulogic;
 358         variable abs1, abs2 : signed(63 downto 0);
 359         variable overflow : std_ulogic;
 360         variable zerohi, zerolo : std_ulogic;
 361         variable msb_a, msb_b : std_ulogic;
 362         variable a_lt : std_ulogic;
 363         variable a_lt_lo : std_ulogic;
 364         variable a_lt_hi : std_ulogic;
 365         variable lv : Execute1ToLoadstore1Type;
 366         variable irq_valid : std_ulogic;
 367         variable exception : std_ulogic;
 368         variable exception_nextpc : std_ulogic;
 369         variable trapval : std_ulogic_vector(4 downto 0);
 370         variable illegal : std_ulogic;
 371         variable is_branch : std_ulogic;
 372         variable is_direct_branch : std_ulogic;
 373         variable taken_branch : std_ulogic;
 374         variable abs_branch : std_ulogic;
 375         variable spr_val : std_ulogic_vector(63 downto 0);
 376         variable addend : std_ulogic_vector(127 downto 0);
 377         variable do_trace : std_ulogic;
 378         variable hold_wr_data : std_ulogic;
 379         variable f : Execute1ToFetch1Type;
 380         variable fv : Execute1ToFPUType;
 381     begin
 382         sum_with_carry := (others => '0');
 383         newcrf := (others => '0');
 384         is_branch := '0';
 385         is_direct_branch := '0';
 386         taken_branch := '0';
 387         abs_branch := '0';
 388         hold_wr_data := '0';
 389
 390         v := r;
 391         v.e := Execute1ToWritebackInit;
 392         v.redirect := '0';
 393         v.abs_br := '0';
 394         v.do_intr := '0';
 395         v.vector := 0;
 396         v.br_offset := (others => '0');
 397         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 398                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 399         v.taken_br := '0';
 400         v.br_last := '0';
 401
 402         lv := Execute1ToLoadstore1Init;
 403         fv := Execute1ToFPUInit;
 404
 405         -- XER forwarding. To avoid having to track XER hazards, we use
 406         -- the previously latched value.  Since the XER common bits
 407         -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 408         -- handled here, we can just forward the result being sent to
 409         -- writeback.
 410         if r.e.write_xerc_enable = '1' or r.busy = '1' then
 411             v.e.xerc := r.e.xerc;
 412         else
 413             v.e.xerc := e_in.xerc;
 414         end if;
 415
 416         cr_in <= e_in.cr;
 417
 418         v.mul_in_progress := '0';
 419         v.div_in_progress := '0';
 420         v.cntz_in_progress := '0';
 421         v.mul_finish := '0';
 422
 423         spr_result <= (others => '0');
 424         spr_val := (others => '0');
 425
 426         -- Main adder
 427         if e_in.invert_a = '0' then
 428             a_inv := a_in;
 429         else
 430             a_inv := not a_in;
 431         end if;
 432         if e_in.addm1 = '0' then
 433             b_or_m1 := b_in;
 434         else
 435             b_or_m1 := (others => '1');
 436         end if;
 437         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 438                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 439         adder_result <= sum_with_carry(63 downto 0);
 440         carry_32 := sum_with_carry(32) xor a_inv(32) xor b_in(32);
 441         carry_64 := sum_with_carry(64);
 442
 443         -- signals to multiply and divide units
 444         sign1 := '0';
 445         sign2 := '0';
 446         if e_in.is_signed = '1' then
 447             if e_in.is_32bit = '1' then
 448                 sign1 := a_in(31);
 449                 sign2 := b_in(31);
 450             else
 451                 sign1 := a_in(63);
 452                 sign2 := b_in(63);
 453             end if;
 454         end if;
 455         -- take absolute values
 456         if sign1 = '0' then
 457             abs1 := signed(a_in);
 458         else
 459             abs1 := - signed(a_in);
 460         end if;
 461         if sign2 = '0' then
 462             abs2 := signed(b_in);
 463         else
 464             abs2 := - signed(b_in);
 465         end if;
 466
 467         -- Interface to multiply and divide units
 468         x_to_multiply <= MultiplyInputInit;
 469         x_to_multiply.is_32bit <= e_in.is_32bit;
 470
 471         x_to_divider <= Execute1ToDividerInit;
 472         x_to_divider.is_signed <= e_in.is_signed;
 473         x_to_divider.is_32bit <= e_in.is_32bit;
 474         if e_in.insn_type = OP_MOD then
 475             x_to_divider.is_modulus <= '1';
 476         end if;
 477
 478         addend := (others => '0');
 479         if e_in.insn(26) = '0' then
 480             -- integer multiply-add, major op 4 (if it is a multiply)
 481             addend(63 downto 0) := c_in;
 482             if e_in.is_signed = '1' then
 483                 addend(127 downto 64) := (others => c_in(63));
 484             end if;
 485         end if;
 486         if (sign1 xor sign2) = '1' then
 487             addend := not addend;
 488         end if;
 489
 490         x_to_multiply.not_result <= sign1 xor sign2;
 491         x_to_multiply.addend <= addend;
 492         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 493         if e_in.is_32bit = '0' then
 494             -- 64-bit forms
 495             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 496             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 497             if e_in.insn_type = OP_DIVE then
 498                 x_to_divider.is_extended <= '1';
 499             end if;
 500             x_to_divider.dividend <= std_ulogic_vector(abs1);
 501             x_to_divider.divisor <= std_ulogic_vector(abs2);
 502         else
 503             -- 32-bit forms
 504             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 505             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 506             x_to_divider.is_extended <= '0';
 507             if e_in.insn_type = OP_DIVE then   -- extended forms
 508                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 509             else
 510                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 511             end if;
 512             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 513         end if;
 514
 515         case current.sub_select(1 downto 0) is
 516             when "00" =>
 517                 muldiv_result <= multiply_to_x.result(63 downto 0);
 518             when "01" =>
 519                 muldiv_result <= multiply_to_x.result(127 downto 64);
 520             when "10" =>
 521                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 522                                  multiply_to_x.result(63 downto 32);
 523             when others =>
 524                 muldiv_result <= divider_to_x.write_reg_data;
 525         end case;
 526
 527         -- Compute misc_result
 528         case current.sub_select is
 529             when "000" =>
 530                 misc_result <= (others => '0');
 531             when "001" =>
 532                 -- addg6s
 533                 addg6s := (others => '0');
 534                 for i in 0 to 14 loop
 535                     lo := i * 4;
 536                     hi := (i + 1) * 4;
 537                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 538                         addg6s(lo + 3 downto lo) := "0110";
 539                     end if;
 540                 end loop;
 541                 if sum_with_carry(64) = '0' then
 542                     addg6s(63 downto 60) := "0110";
 543                 end if;
 544                 misc_result <= addg6s;
 545             when "010" =>
 546                 -- isel
 547                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 548                 if cr_in(31-crbit) = '1' then
 549                     isel_result := a_in;
 550                 else
 551                     isel_result := b_in;
 552                 end if;
 553                 misc_result <= isel_result;
 554             when "011" =>
 555                 -- darn
 556                 darn := (others => '1');
 557                 if random_err = '0' then
 558                     case e_in.insn(17 downto 16) is
 559                         when "00" =>
 560                             darn := x"00000000" & random_cond(31 downto 0);
 561                         when "10" =>
 562                             darn := random_raw;
 563                         when others =>
 564                             darn := random_cond;
 565                     end case;
 566                 end if;
 567                 misc_result <= darn;
 568             when "100" =>
 569                 -- mfmsr
 570                 misc_result <= ctrl.msr;
 571             when "101" =>
 572                 if e_in.insn(20) = '0' then
 573                     -- mfcr
 574                     mfcr_result := x"00000000" & cr_in;
 575                 else
 576                     -- mfocrf
 577                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 578                     mfcr_result := (others => '0');
 579                     for i in 0 to 7 loop
 580                         lo := (7-i)*4;
 581                         hi := lo + 3;
 582                         if crnum = i then
 583                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 584                         end if;
 585                     end loop;
 586                 end if;
 587                 misc_result <= mfcr_result;
 588             when "110" =>
 589                 -- setb
 590                 bfa := insn_bfa(e_in.insn);
 591                 crbit := to_integer(unsigned(bfa)) * 4;
 592                 setb_result := (others => '0');
 593                 if cr_in(31 - crbit) = '1' then
 594                     setb_result := (others => '1');
 595                 elsif cr_in(30 - crbit) = '1' then
 596                     setb_result(0) := '1';
 597                 end if;
 598                 misc_result <= setb_result;
 599             when others =>
 600                 misc_result <= (others => '0');
 601         end case;
 602
 603         -- compute comparison results
 604         -- Note, we have done RB - RA, not RA - RB
 605         if e_in.insn_type = OP_CMP then
 606             l := insn_l(e_in.insn);
 607         else
 608             l := not e_in.is_32bit;
 609         end if;
 610         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 611         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 612         if zerolo = '1' and (l = '0' or zerohi = '1') then
 613             -- values are equal
 614             trapval := "00100";
 615         else
 616             a_lt_lo := '0';
 617             a_lt_hi := '0';
 618             if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
 619                 a_lt_lo := '1';
 620             end if;
 621             if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
 622                 a_lt_hi := '1';
 623             end if;
 624             if l = '1' then
 625                 -- 64-bit comparison
 626                 msb_a := a_in(63);
 627                 msb_b := b_in(63);
 628                 a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
 629             else
 630                 -- 32-bit comparison
 631                 msb_a := a_in(31);
 632                 msb_b := b_in(31);
 633                 a_lt := a_lt_lo;
 634             end if;
 635             if msb_a /= msb_b then
 636                 -- Comparison is clear from MSB difference.
 637                 -- for signed, 0 is greater; for unsigned, 1 is greater
 638                 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 639             else
 640                 -- MSBs are equal, so signed and unsigned comparisons give the
 641                 -- same answer.
 642                 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 643             end if;
 644         end if;
 645
 646         ctrl_tmp <= ctrl;
 647         -- FIXME: run at 512MHz not core freq
 648         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 649         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 650
 651         irq_valid := '0';
 652         if ctrl.msr(MSR_EE) = '1' then
 653             if ctrl.dec(63) = '1' then
 654                 v.vector := 16#900#;
 655                 report "IRQ valid: DEC";
 656                 irq_valid := '1';
 657             elsif ext_irq_in = '1' then
 658                 v.vector := 16#500#;
 659                 report "IRQ valid: External";
 660                 irq_valid := '1';
 661             end if;
 662         end if;
 663
 664         v.terminate := '0';
 665         icache_inval <= '0';
 666         v.busy := '0';
 667
 668         -- Next insn adder used in a couple of places
 669         next_nia <= std_ulogic_vector(unsigned(e_in.nia) + 4);
 670
 671         -- rotator control signals
 672         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 673         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 674         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 675         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 676
 677         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 678         ctrl_tmp.irq_state <= WRITE_SRR0;
 679         exception := '0';
 680         illegal := '0';
 681         exception_nextpc := '0';
 682         v.e.exc_write_enable := '0';
 683         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 684         if valid_in = '1' then
 685             v.e.exc_write_data := e_in.nia;
 686             v.last_nia := e_in.nia;
 687         else
 688             v.e.exc_write_data := r.last_nia;
 689         end if;
 690
 691         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 692         v.e.instr_tag := current.instr_tag;
 693
 694         do_trace := valid_in and ctrl.msr(MSR_SE);
 695         if valid_in = '1' then
 696             v.prev_op := e_in.insn_type;
 697         end if;
 698
 699         -- Determine if there is any exception to be taken
 700         -- before/instead of executing this instruction
 701         if valid_in = '1' and e_in.second = '0' then
 702             if HAS_FPU and r.fp_exception_next = '1' then
 703                 -- This is used for FP-type program interrupts that
 704                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 705                 exception := '1';
 706                 v.vector := 16#700#;
 707                 ctrl_tmp.srr1(63 - 43) <= '1';
 708                 ctrl_tmp.srr1(63 - 47) <= '1';
 709             elsif r.trace_next = '1' then
 710                 -- Generate a trace interrupt rather than executing the next instruction
 711                 -- or taking any asynchronous interrupt
 712                 exception := '1';
 713                 v.vector := 16#d00#;
 714                 ctrl_tmp.srr1(63 - 33) <= '1';
 715                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 716                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 717                     ctrl_tmp.srr1(63 - 35) <= '1';
 718                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 719                     ctrl_tmp.srr1(63 - 36) <= '1';
 720                 end if;
 721
 722             elsif irq_valid = '1' then
 723                 -- Don't deliver the interrupt until we have a valid instruction
 724                 -- coming in, so we have a valid NIA to put in SRR0.
 725                 exception := '1';
 726
 727             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 728                 -- generate a program interrupt
 729                 exception := '1';
 730                 v.vector := 16#700#;
 731                 -- set bit 45 to indicate privileged instruction type interrupt
 732                 ctrl_tmp.srr1(63 - 45) <= '1';
 733                 report "privileged instruction";
 734
 735             elsif not HAS_FPU and e_in.fac = FPU then
 736                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 737                 illegal := '1';
 738
 739             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 740                 -- generate a floating-point unavailable interrupt
 741                 exception := '1';
 742                 v.vector := 16#800#;
 743                 report "FP unavailable interrupt";
 744             end if;
 745         end if;
 746
 747         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 748             v.cur_instr := e_in;
 749             v.next_lr := next_nia;
 750             v.e.valid := '1';
 751
 752             case_0: case e_in.insn_type is
 753
 754             when OP_ILLEGAL =>
 755                 -- we need two cycles to write srr0 and 1
 756                 -- will need more when we have to write HEIR
 757                 illegal := '1';
 758             when OP_SC =>
 759                 -- check bit 1 of the instruction is 1 so we know this is sc;
 760                 -- 0 would mean scv, so generate an illegal instruction interrupt
 761                 -- we need two cycles to write srr0 and 1
 762                 if e_in.insn(1) = '1' then
 763                     exception := '1';
 764                     exception_nextpc := '1';
 765                     v.vector := 16#C00#;
 766                     report "sc";
 767                 else
 768                     illegal := '1';
 769                 end if;
 770             when OP_ATTN =>
 771                 -- check bits 1-10 of the instruction to make sure it's attn
 772                 -- if not then it is illegal
 773                 if e_in.insn(10 downto 1) = "0100000000" then
 774                     v.terminate := '1';
 775                     report "ATTN";
 776                 else
 777                     illegal := '1';
 778                 end if;
 779             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 780                 -- Do nothing
 781             when OP_ADD =>
 782                 if e_in.output_carry = '1' then
 783                     if e_in.input_carry /= OV then
 784                         set_carry(v.e, carry_32, carry_64);
 785                     else
 786                         v.e.xerc.ov := carry_64;
 787                         v.e.xerc.ov32 := carry_32;
 788                         v.e.write_xerc_enable := '1';
 789                     end if;
 790                 end if;
 791                 if e_in.oe = '1' then
 792                     set_ov(v.e,
 793                            calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 794                            calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 795                 end if;
 796             when OP_CMP =>
 797                 -- CMP and CMPL instructions
 798                 if e_in.is_signed = '1' then
 799                     newcrf := trapval(4 downto 2) & v.e.xerc.so;
 800                 else
 801                     newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 802                 end if;
 803                 bf := insn_bf(e_in.insn);
 804                 crnum := to_integer(unsigned(bf));
 805                 v.e.write_cr_mask := num_to_fxm(crnum);
 806                 for i in 0 to 7 loop
 807                     lo := i*4;
 808                     hi := lo + 3;
 809                     v.e.write_cr_data(hi downto lo) := newcrf;
 810                 end loop;
 811             when OP_TRAP =>
 812                 -- trap instructions (tw, twi, td, tdi)
 813                 v.vector := 16#700#;
 814                 -- set bit 46 to say trap occurred
 815                 ctrl_tmp.srr1(63 - 46) <= '1';
 816                 if or (trapval and insn_to(e_in.insn)) = '1' then
 817                     -- generate trap-type program interrupt
 818                     exception := '1';
 819                     report "trap";
 820                 end if;
 821             when OP_ADDG6S =>
 822             when OP_CMPRB =>
 823                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 824                 bf := insn_bf(e_in.insn);
 825                 crnum := to_integer(unsigned(bf));
 826                 v.e.write_cr_mask := num_to_fxm(crnum);
 827                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 828                                      newcrf & newcrf & newcrf & newcrf;
 829             when OP_CMPEQB =>
 830                 newcrf := ppc_cmpeqb(a_in, b_in);
 831                 bf := insn_bf(e_in.insn);
 832                 crnum := to_integer(unsigned(bf));
 833                 v.e.write_cr_mask := num_to_fxm(crnum);
 834                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 835                                      newcrf & newcrf & newcrf & newcrf;
 836             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 837                     OP_BPERM | OP_BCD =>
 838
 839             when OP_B =>
 840                 is_branch := '1';
 841                 taken_branch := '1';
 842                 is_direct_branch := '1';
 843                 abs_branch := e_in.br_abs;
 844                 if ctrl.msr(MSR_BE) = '1' then
 845                     do_trace := '1';
 846                 end if;
 847             when OP_BC | OP_BCREG =>
 848                 -- read_data1 is CTR
 849                 -- for OP_BCREG, read_data2 is target register (CTR, LR or TAR)
 850                 -- If this instruction updates both CTR and LR, then it is
 851                 -- doubled; the first instruction decrements CTR and determines
 852                 -- whether the branch is taken, and the second does the
 853                 -- redirect and the LR update.
 854                 bo := insn_bo(e_in.insn);
 855                 bi := insn_bi(e_in.insn);
 856                 if e_in.second = '0' then
 857                     taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 858                 else
 859                     taken_branch := r.br_taken;
 860                 end if;
 861                 v.br_taken := taken_branch;
 862                 abs_branch := e_in.br_abs;
 863                 if e_in.repeat = '0' or e_in.second = '1' then
 864                     is_branch := '1';
 865                     if e_in.insn_type = OP_BC then
 866                         is_direct_branch := '1';
 867                     end if;
 868                     if ctrl.msr(MSR_BE) = '1' then
 869                         do_trace := '1';
 870                     end if;
 871                 end if;
 872
 873             when OP_RFID =>
 874                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 875                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 876                 -- Can't use msr_copy here because the partial function MSR
 877                 -- bits should be left unchanged, not zeroed.
 878                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 879                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 880                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 881                 if a_in(MSR_PR) = '1' then
 882                     ctrl_tmp.msr(MSR_EE) <= '1';
 883                     ctrl_tmp.msr(MSR_IR) <= '1';
 884                     ctrl_tmp.msr(MSR_DR) <= '1';
 885                 end if;
 886                 -- mark this as a branch so CFAR gets updated
 887                 is_branch := '1';
 888                 taken_branch := '1';
 889                 abs_branch := '1';
 890                 if HAS_FPU then
 891                     v.fp_exception_next := fp_in.exception and
 892                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 893                 end if;
 894                 do_trace := '0';
 895
 896             when OP_CNTZ =>
 897                 v.e.valid := '0';
 898                 v.cntz_in_progress := '1';
 899                 v.busy := '1';
 900             when OP_ISEL =>
 901             when OP_CROP =>
 902                 cr_op := insn_cr(e_in.insn);
 903                 if cr_op(0) = '0' then -- MCRF
 904                     bf := insn_bf(e_in.insn);
 905                     bfa := insn_bfa(e_in.insn);
 906                     crnum := to_integer(unsigned(bf));
 907                     scrnum := to_integer(unsigned(bfa));
 908                     v.e.write_cr_mask := num_to_fxm(crnum);
 909                     for i in 0 to 7 loop
 910                         lo := (7-i)*4;
 911                         hi := lo + 3;
 912                         if i = scrnum then
 913                             newcrf := cr_in(hi downto lo);
 914                         end if;
 915                     end loop;
 916                     for i in 0 to 7 loop
 917                         lo := i*4;
 918                         hi := lo + 3;
 919                         v.e.write_cr_data(hi downto lo) := newcrf;
 920                     end loop;
 921                 else
 922                     bt := insn_bt(e_in.insn);
 923                     ba := insn_ba(e_in.insn);
 924                     bb := insn_bb(e_in.insn);
 925                     btnum := 31 - to_integer(unsigned(bt));
 926                     banum := 31 - to_integer(unsigned(ba));
 927                     bbnum := 31 - to_integer(unsigned(bb));
 928                     -- Bits 5-8 of cr_op give the truth table of the requested
 929                     -- logical operation
 930                     cr_operands := cr_in(banum) & cr_in(bbnum);
 931                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 932                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 933                     for i in 0 to 31 loop
 934                         if i = btnum then
 935                             v.e.write_cr_data(i) := crresult;
 936                         else
 937                             v.e.write_cr_data(i) := cr_in(i);
 938                         end if;
 939                     end loop;
 940                 end if;
 941             when OP_MCRXRX =>
 942                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 943                 bf := insn_bf(e_in.insn);
 944                 crnum := to_integer(unsigned(bf));
 945                 v.e.write_cr_mask := num_to_fxm(crnum);
 946                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 947                                      newcrf & newcrf & newcrf & newcrf;
 948             when OP_DARN =>
 949             when OP_MFMSR =>
 950             when OP_MFSPR =>
 951                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 952                     "=" & to_hstring(a_in);
 953                 if is_fast_spr(e_in.read_reg1) = '1' then
 954                     spr_val := a_in;
 955                     if decode_spr_num(e_in.insn) = SPR_XER then
 956                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 957                         spr_val(63 downto 32) := (others => '0');
 958                         spr_val(63-32) := v.e.xerc.so;
 959                         spr_val(63-33) := v.e.xerc.ov;
 960                         spr_val(63-34) := v.e.xerc.ca;
 961                         spr_val(63-35 downto 63-43) := "000000000";
 962                         spr_val(63-44) := v.e.xerc.ov32;
 963                         spr_val(63-45) := v.e.xerc.ca32;
 964                     end if;
 965                 else
 966                     spr_val := c_in;
 967                     case decode_spr_num(e_in.insn) is
 968                     when SPR_TB =>
 969                         spr_val := ctrl.tb;
 970                     when SPR_TBU =>
 971                         spr_val(63 downto 32) := (others => '0');
 972                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 973                     when SPR_DEC =>
 974                         spr_val := ctrl.dec;
 975                     when SPR_CFAR =>
 976                         spr_val := ctrl.cfar;
 977                     when SPR_PVR =>
 978                         spr_val(63 downto 32) := (others => '0');
 979                         spr_val(31 downto 0) := PVR_MICROWATT;
 980                     when 724 =>     -- LOG_ADDR SPR
 981                         spr_val := log_wr_addr & r.log_addr_spr;
 982                     when 725 =>     -- LOG_DATA SPR
 983                         spr_val := log_rd_data;
 984                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 985                     when others =>
 986                         -- mfspr from unimplemented SPRs should be a nop in
 987                         -- supervisor mode and a program interrupt for user mode
 988                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
 989                             illegal := '1';
 990                         end if;
 991                     end case;
 992                 end if;
 993                 spr_result <= spr_val;
 994
 995             when OP_MFCR =>
 996             when OP_MTCRF =>
 997                 if e_in.insn(20) = '0' then
 998                     -- mtcrf
 999                     v.e.write_cr_mask := insn_fxm(e_in.insn);
1000                 else
1001                     -- mtocrf: We require one hot priority encoding here
1002                     crnum := fxm_to_num(insn_fxm(e_in.insn));
1003                     v.e.write_cr_mask := num_to_fxm(crnum);
1004                 end if;
1005                 v.e.write_cr_data := c_in(31 downto 0);
1006             when OP_MTMSRD =>
1007                 if e_in.insn(16) = '1' then
1008                     -- just update EE and RI
1009                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
1010                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
1011                 else
1012                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
1013                     -- and 63 (LE) (IBM bit numbering)
1014                     if e_in.is_32bit = '0' then
1015                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1016                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1017                     end if;
1018                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1019                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1020                     if c_in(MSR_PR) = '1' then
1021                         ctrl_tmp.msr(MSR_EE) <= '1';
1022                         ctrl_tmp.msr(MSR_IR) <= '1';
1023                         ctrl_tmp.msr(MSR_DR) <= '1';
1024                     end if;
1025                     if HAS_FPU then
1026                         v.fp_exception_next := fp_in.exception and
1027                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1028                     end if;
1029                 end if;
1030             when OP_MTSPR =>
1031                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1032                     "=" & to_hstring(c_in);
1033                 if is_fast_spr(e_in.write_reg) then
1034                     if decode_spr_num(e_in.insn) = SPR_XER then
1035                         v.e.xerc.so := c_in(63-32);
1036                         v.e.xerc.ov := c_in(63-33);
1037                         v.e.xerc.ca := c_in(63-34);
1038                         v.e.xerc.ov32 := c_in(63-44);
1039                         v.e.xerc.ca32 := c_in(63-45);
1040                         v.e.write_xerc_enable := '1';
1041                     end if;
1042                 else
1043                     -- slow spr
1044                     case decode_spr_num(e_in.insn) is
1045                     when SPR_DEC =>
1046                         ctrl_tmp.dec <= c_in;
1047                     when 724 =>     -- LOG_ADDR SPR
1048                         v.log_addr_spr := c_in(31 downto 0);
1049                     when others =>
1050                         -- mtspr to unimplemented SPRs should be a nop in
1051                         -- supervisor mode and a program interrupt for user mode
1052                         if ctrl.msr(MSR_PR) = '1' then
1053                             illegal := '1';
1054                         end if;
1055                     end case;
1056                 end if;
1057             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1058                 if e_in.output_carry = '1' then
1059                     set_carry(v.e, rotator_carry, rotator_carry);
1060                 end if;
1061             when OP_SETB =>
1062
1063             when OP_ISYNC =>
1064                 v.redirect := '1';
1065                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1066
1067             when OP_ICBI =>
1068                 icache_inval <= '1';
1069
1070             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1071                 v.e.valid := '0';
1072                 v.mul_in_progress := '1';
1073                 v.busy := '1';
1074                 x_to_multiply.valid <= '1';
1075
1076             when OP_DIV | OP_DIVE | OP_MOD =>
1077                 v.e.valid := '0';
1078                 v.div_in_progress := '1';
1079                 v.busy := '1';
1080                 x_to_divider.valid <= '1';
1081
1082             when others =>
1083                 v.terminate := '1';
1084                 report "illegal";
1085             end case;
1086
1087             -- Mispredicted branches cause a redirect
1088             if is_branch = '1' then
1089                 if taken_branch = '1' then
1090                     ctrl_tmp.cfar <= e_in.nia;
1091                 end if;
1092                 if taken_branch = '1' then
1093                     v.br_offset := b_in;
1094                     v.abs_br := abs_branch;
1095                 else
1096                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1097                 end if;
1098                 if taken_branch /= e_in.br_pred then
1099                     v.redirect := '1';
1100                 end if;
1101                 v.br_last := is_direct_branch;
1102                 v.taken_br := taken_branch;
1103             end if;
1104
1105         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1106             -- instruction for other units, i.e. LDST
1107             if e_in.unit = LDST then
1108                 lv.valid := '1';
1109             elsif e_in.unit = NONE then
1110                 illegal := '1';
1111             elsif HAS_FPU and e_in.unit = FPU then
1112                 fv.valid := '1';
1113             end if;
1114             -- Handling an ITLB miss doesn't count as having executed an instruction
1115             if e_in.insn_type = OP_FETCH_FAILED then
1116                 do_trace := '0';
1117             end if;
1118         end if;
1119
1120         -- The following cases all occur when r.busy = 1 and therefore
1121         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1122         -- the cases above which depend on valid_in = 1.
1123
1124         if ctrl.irq_state = WRITE_SRR1 then
1125             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
1126             v.e.exc_write_data := ctrl.srr1;
1127             v.e.exc_write_enable := '1';
1128             ctrl_tmp.msr(MSR_SF) <= '1';
1129             ctrl_tmp.msr(MSR_EE) <= '0';
1130             ctrl_tmp.msr(MSR_PR) <= '0';
1131             ctrl_tmp.msr(MSR_SE) <= '0';
1132             ctrl_tmp.msr(MSR_BE) <= '0';
1133             ctrl_tmp.msr(MSR_FP) <= '0';
1134             ctrl_tmp.msr(MSR_FE0) <= '0';
1135             ctrl_tmp.msr(MSR_FE1) <= '0';
1136             ctrl_tmp.msr(MSR_IR) <= '0';
1137             ctrl_tmp.msr(MSR_DR) <= '0';
1138             ctrl_tmp.msr(MSR_RI) <= '0';
1139             ctrl_tmp.msr(MSR_LE) <= '1';
1140             v.trace_next := '0';
1141             v.fp_exception_next := '0';
1142             report "Writing SRR1: " & to_hstring(ctrl.srr1);
1143
1144         elsif r.cntz_in_progress = '1' then
1145             -- cnt[lt]z always takes two cycles
1146             v.e.valid := '1';
1147         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1148             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1149                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1150                 if r.mul_in_progress = '1' then
1151                     overflow := '0';
1152                 else
1153                     overflow := divider_to_x.overflow;
1154                 end if;
1155                 if r.mul_in_progress = '1' and current.oe = '1' then
1156                     -- have to wait until next cycle for overflow indication
1157                     v.mul_finish := '1';
1158                     v.busy := '1';
1159                 else
1160                     v.e.write_xerc_enable := current.oe;
1161                     -- We must test oe because the RC update code in writeback
1162                     -- will use the xerc value to set CR0:SO so we must not clobber
1163                     -- xerc if OE wasn't set.
1164                     if current.oe = '1' then
1165                         v.e.xerc.ov := overflow;
1166                         v.e.xerc.ov32 := overflow;
1167                         if overflow = '1' then
1168                             v.e.xerc.so := '1';
1169                         end if;
1170                     end if;
1171                     v.e.valid := '1';
1172                 end if;
1173             else
1174                 v.busy := '1';
1175                 v.mul_in_progress := r.mul_in_progress;
1176                 v.div_in_progress := r.div_in_progress;
1177             end if;
1178         elsif r.mul_finish = '1' then
1179             hold_wr_data := '1';
1180             v.e.write_xerc_enable := current.oe;
1181             v.e.xerc.ov := multiply_to_x.overflow;
1182             v.e.xerc.ov32 := multiply_to_x.overflow;
1183             if multiply_to_x.overflow = '1' then
1184                 v.e.xerc.so := '1';
1185             end if;
1186             v.e.valid := '1';
1187         end if;
1188
1189         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1190         -- be set during the execution of a FP instruction.
1191         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1192         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1193         if HAS_FPU and fp_in.interrupt = '1' then
1194             v.vector := 16#700#;
1195             ctrl_tmp.srr1(63 - 43) <= '1';
1196             exception := '1';
1197         end if;
1198
1199         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1200             exception := '1';
1201             v.vector := 16#700#;
1202             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1203             -- set bit 44 to indicate we have an illegal
1204             ctrl_tmp.srr1(63 - 44) <= '1';
1205             report "illegal";
1206         end if;
1207         if exception = '1' then
1208             v.e.exc_write_enable := '1';
1209             if exception_nextpc = '1' then
1210                 v.e.exc_write_data := next_nia;
1211             end if;
1212         end if;
1213
1214         -- generate DSI or DSegI for load/store exceptions
1215         -- or ISI or ISegI for instruction fetch exceptions
1216         if l_in.exception = '1' then
1217             if l_in.alignment = '1' then
1218                 v.vector := 16#600#;
1219             elsif l_in.instr_fault = '0' then
1220                 if l_in.segment_fault = '0' then
1221                     v.vector := 16#300#;
1222                 else
1223                     v.vector := 16#380#;
1224                 end if;
1225             else
1226                 if l_in.segment_fault = '0' then
1227                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1228                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1229                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1230                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1231                     v.vector := 16#400#;
1232                 else
1233                     v.vector := 16#480#;
1234                 end if;
1235             end if;
1236             v.e.exc_write_enable := '1';
1237             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1238             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1239         end if;
1240
1241         if exception = '1' or l_in.exception = '1' then
1242             ctrl_tmp.irq_state <= WRITE_SRR1;
1243             v.redirect := '1';
1244             v.do_intr := '1';
1245         end if;
1246
1247         if do_trace = '1' then
1248             v.trace_next := '1';
1249         end if;
1250
1251         if hold_wr_data = '0' then
1252             v.e.write_data := alu_result;
1253         else
1254             v.e.write_data := r.e.write_data;
1255         end if;
1256         v.e.write_reg := current.write_reg;
1257         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1258         v.e.write_cr_enable := current.output_cr and v.e.valid and not exception;
1259         v.e.rc := current.rc and v.e.valid and not exception;
1260
1261         bypass_data.tag.valid <= current.instr_tag.valid and current.write_reg_enable and v.e.valid;
1262         bypass_data.tag.tag <= current.instr_tag.tag;
1263         bypass_data.data <= v.e.write_data;
1264
1265         bypass_cr_data.tag.valid <= current.instr_tag.valid and current.output_cr and v.e.valid;
1266         bypass_cr_data.tag.tag <= current.instr_tag.tag;
1267         for i in 0 to 7 loop
1268             if v.e.write_cr_mask(i) = '1' then
1269                 bypass_cr_data.data(i*4 + 3 downto i*4) <= v.e.write_cr_data(i*4 + 3 downto i*4);
1270             else
1271                 bypass_cr_data.data(i*4 + 3 downto i*4) <= cr_in(i*4 + 3 downto i*4);
1272             end if;
1273         end loop;
1274
1275         -- Defer completion for one cycle when redirecting.
1276         -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
1277         if v.redirect = '1' then
1278             v.busy := '1';
1279             v.e.valid := '0';
1280         end if;
1281         if r.redirect = '1' then
1282             v.e.valid := '1';
1283         end if;
1284
1285         -- Outputs to fetch1
1286         f.redirect := r.redirect;
1287         f.br_nia := r.last_nia;
1288         f.br_last := r.br_last and not r.do_intr;
1289         f.br_taken := r.taken_br;
1290         if r.do_intr = '1' then
1291             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1292             f.virt_mode := '0';
1293             f.priv_mode := '1';
1294             -- XXX need an interrupt LE bit here, e.g. from LPCR
1295             f.big_endian := '0';
1296             f.mode_32bit := '0';
1297         else
1298             if r.abs_br = '1' then
1299                 f.redirect_nia := r.br_offset;
1300             else
1301                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1302             end if;
1303             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1304             f.virt_mode := r.redir_mode(3);
1305             f.priv_mode := r.redir_mode(2);
1306             f.big_endian := r.redir_mode(1);
1307             f.mode_32bit := r.redir_mode(0);
1308         end if;
1309
1310         -- Outputs to loadstore1 (async)
1311         lv.op := e_in.insn_type;
1312         lv.nia := e_in.nia;
1313         lv.instr_tag := e_in.instr_tag;
1314         lv.addr1 := a_in;
1315         lv.addr2 := b_in;
1316         lv.data := c_in;
1317         lv.write_reg := e_in.write_reg;
1318         lv.length := e_in.data_len;
1319         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1320         lv.sign_extend := e_in.sign_extend;
1321         lv.update := e_in.update;
1322         lv.xerc := v.e.xerc;
1323         lv.reserve := e_in.reserve;
1324         lv.rc := e_in.rc;
1325         lv.insn := e_in.insn;
1326         -- decode l*cix and st*cix instructions here
1327         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1328             e_in.insn(5 downto 1) = "10101" then
1329             lv.ci := '1';
1330         end if;
1331         lv.virt_mode := ctrl.msr(MSR_DR);
1332         lv.priv_mode := not ctrl.msr(MSR_PR);
1333         lv.mode_32bit := not ctrl.msr(MSR_SF);
1334         lv.is_32bit := e_in.is_32bit;
1335         lv.repeat := e_in.repeat;
1336         lv.second := e_in.second;
1337
1338         -- Outputs to FPU
1339         fv.op := e_in.insn_type;
1340         fv.nia := e_in.nia;
1341         fv.insn := e_in.insn;
1342         fv.itag := e_in.instr_tag;
1343         fv.single := e_in.is_32bit;
1344         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1345         fv.fra := a_in;
1346         fv.frb := b_in;
1347         fv.frc := c_in;
1348         fv.frt := e_in.write_reg;
1349         fv.rc := e_in.rc;
1350         fv.out_cr := e_in.output_cr;
1351
1352         -- Update registers
1353         rin <= v;
1354
1355         -- update outputs
1356         f_out <= f;
1357         l_out <= lv;
1358         e_out <= r.e;
1359         fp_out <= fv;
1360         flush_out <= f_out.redirect;
1361
1362         exception_log <= exception;
1363         irq_valid_log <= irq_valid;
1364     end process;
1365
1366     e1_log: if LOG_LENGTH > 0 generate
1367         signal log_data : std_ulogic_vector(14 downto 0);
1368     begin
1369         ex1_log : process(clk)
1370         begin
1371             if rising_edge(clk) then
1372                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1373                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1374                             exception_log &
1375                             irq_valid_log &
1376                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1377                             "000" &
1378                             r.e.write_enable &
1379                             r.e.valid &
1380                             f_out.redirect &
1381                             r.busy &
1382                             flush_out;
1383             end if;
1384         end process;
1385         log_out <= log_data;
1386     end generate;
1387 end architecture behaviour;