fpga/top-genesys2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library unisim;
   6 use unisim.vcomponents.all;
   7
   8 library work;
   9 use work.wishbone_types.all;
  10
  11 entity toplevel is
  12     generic (
  13         MEMORY_SIZE   : integer := 16384;
  14         RAM_INIT_FILE : string   := "firmware.hex";
  15         RESET_LOW     : boolean  := true;
  16         CLK_FREQUENCY : positive := 100000000;
  17         USE_LITEDRAM  : boolean  := false;
  18         NO_BRAM       : boolean  := false;
  19         DISABLE_FLATTEN_CORE : boolean := false;
  20         SPI_FLASH_OFFSET   : integer := 10485760;
  21         SPI_FLASH_DEF_CKDV : natural := 1;
  22         SPI_FLASH_DEF_QUAD : boolean := true;
  23         LOG_LENGTH         : natural := 2048;
  24         UART_IS_16550      : boolean := true
  25         );
  26     port(
  27         clk200_p   : in  std_ulogic;
  28         clk200_n   : in  std_ulogic;
  29         ext_rst    : in  std_ulogic;
  30
  31         -- UART0 signals:
  32         uart_main_tx : out std_ulogic;
  33         uart_main_rx : in  std_ulogic;
  34
  35         -- LEDs
  36         led0    : out std_logic;
  37         led1    : out std_logic;
  38         led2    : out std_logic;
  39         led3    : out std_logic;
  40
  41         -- SPI
  42         spi_flash_cs_n   : out std_ulogic;
  43         spi_flash_mosi   : inout std_ulogic;
  44         spi_flash_miso   : inout std_ulogic;
  45         spi_flash_wp_n   : inout std_ulogic;
  46         spi_flash_hold_n : inout std_ulogic;
  47
  48         -- DRAM wires
  49         ddram_a       : out std_logic_vector(14 downto 0);
  50         ddram_ba      : out std_logic_vector(2 downto 0);
  51         ddram_ras_n   : out std_logic;
  52         ddram_cas_n   : out std_logic;
  53         ddram_we_n    : out std_logic;
  54         ddram_cs_n    : out std_ulogic;
  55         ddram_dm      : out std_logic_vector(3 downto 0);
  56         ddram_dq      : inout std_logic_vector(31 downto 0);
  57         ddram_dqs_p   : inout std_logic_vector(3 downto 0);
  58         ddram_dqs_n   : inout std_logic_vector(3 downto 0);
  59         ddram_clk_p   : out std_logic;
  60         ddram_clk_n   : out std_logic;
  61         ddram_cke     : out std_logic;
  62         ddram_odt     : out std_logic;
  63         ddram_reset_n : out std_logic
  64         );
  65 end entity toplevel;
  66
  67 architecture behaviour of toplevel is
  68
  69     -- Internal clock
  70     signal ext_clk : std_ulogic;
  71
  72     -- Reset signals:
  73     signal soc_rst : std_ulogic;
  74     signal pll_rst : std_ulogic;
  75
  76     -- Internal clock signals:
  77     signal system_clk : std_ulogic;
  78     signal system_clk_locked : std_ulogic;
  79
  80     -- DRAM main data wishbone connection
  81     signal wb_dram_in       : wishbone_master_out;
  82     signal wb_dram_out      : wishbone_slave_out;
  83
  84     -- DRAM control wishbone connection
  85     signal wb_ext_io_in        : wb_io_master_out;
  86     signal wb_ext_io_out       : wb_io_slave_out;
  87     signal wb_ext_is_dram_csr  : std_ulogic;
  88     signal wb_ext_is_dram_init : std_ulogic;
  89
  90     -- Control/status
  91     signal core_alt_reset : std_ulogic;
  92
  93     -- SPI flash
  94     signal spi_sck     : std_ulogic;
  95     signal spi_cs_n    : std_ulogic;
  96     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
  97     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
  98     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
  99
 100     -- Fixup various memory sizes based on generics
 101     function get_bram_size return natural is
 102     begin
 103         if USE_LITEDRAM and NO_BRAM then
 104             return 0;
 105         else
 106             return MEMORY_SIZE;
 107         end if;
 108     end function;
 109
 110     function get_payload_size return natural is
 111     begin
 112         if USE_LITEDRAM and NO_BRAM then
 113             return MEMORY_SIZE;
 114         else
 115             return 0;
 116         end if;
 117     end function;
 118
 119     constant BRAM_SIZE    : natural := get_bram_size;
 120     constant PAYLOAD_SIZE : natural := get_payload_size;
 121 begin
 122
 123     -- Main SoC
 124     soc0: entity work.soc
 125         generic map(
 126             MEMORY_SIZE   => BRAM_SIZE,
 127             RAM_INIT_FILE => RAM_INIT_FILE,
 128             SIM           => false,
 129             CLK_FREQ      => CLK_FREQUENCY,
 130             HAS_DRAM      => USE_LITEDRAM,
 131             DRAM_SIZE     => 1024 * 1024 * 1024,
 132             DRAM_INIT_SIZE => PAYLOAD_SIZE,
 133             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
 134             HAS_SPI_FLASH      => true,
 135             SPI_FLASH_DLINES   => 4,
 136             SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
 137             SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
 138             SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
 139             LOG_LENGTH         => LOG_LENGTH,
 140             UART0_IS_16550     => UART_IS_16550
 141             )
 142         port map (
 143             -- System signals
 144             system_clk        => system_clk,
 145             rst               => soc_rst,
 146
 147             -- UART signals
 148             uart0_txd         => uart_main_tx,
 149             uart0_rxd         => uart_main_rx,
 150
 151             -- SPI signals
 152             spi_flash_sck     => spi_sck,
 153             spi_flash_cs_n    => spi_cs_n,
 154             spi_flash_sdat_o  => spi_sdat_o,
 155             spi_flash_sdat_oe => spi_sdat_oe,
 156             spi_flash_sdat_i  => spi_sdat_i,
 157
 158             -- DRAM wishbone
 159             wb_dram_in          => wb_dram_in,
 160             wb_dram_out         => wb_dram_out,
 161             wb_ext_io_in        => wb_ext_io_in,
 162             wb_ext_io_out       => wb_ext_io_out,
 163             wb_ext_is_dram_csr  => wb_ext_is_dram_csr,
 164             wb_ext_is_dram_init => wb_ext_is_dram_init,
 165             alt_reset           => core_alt_reset
 166             );
 167
 168     -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
 169     -- primitive of the FPGA as it's not a normal pin
 170     --
 171     spi_flash_cs_n   <= spi_cs_n;
 172     spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
 173     spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
 174     spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
 175     spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
 176     spi_sdat_i(0)    <= spi_flash_mosi;
 177     spi_sdat_i(1)    <= spi_flash_miso;
 178     spi_sdat_i(2)    <= spi_flash_wp_n;
 179     spi_sdat_i(3)    <= spi_flash_hold_n;
 180
 181     STARTUPE2_INST: STARTUPE2
 182         port map (
 183             CLK => '0',
 184             GSR => '0',
 185             GTS => '0',
 186             KEYCLEARB => '0',
 187             PACK => '0',
 188             USRCCLKO => spi_sck,
 189             USRCCLKTS => '0',
 190             USRDONEO => '1',
 191             USRDONETS => '0'
 192             );
 193
 194     clk200: IBUFDS
 195         port map (
 196             i  => clk200_p,
 197             ib => clk200_n,
 198             o  => ext_clk
 199         );
 200
 201     nodram: if not USE_LITEDRAM generate
 202         signal ddram_clk_dummy : std_ulogic;
 203     begin
 204         reset_controller: entity work.soc_reset
 205             generic map(
 206                 RESET_LOW => RESET_LOW
 207                 )
 208             port map(
 209                 ext_clk => ext_clk,
 210                 pll_clk => system_clk,
 211                 pll_locked_in => system_clk_locked,
 212                 ext_rst_in => ext_rst,
 213                 pll_rst_out => pll_rst,
 214                 rst_out => soc_rst
 215                 );
 216
 217         clkgen: entity work.clock_generator
 218             generic map(
 219                 CLK_INPUT_HZ => 200000000,
 220                 CLK_OUTPUT_HZ => CLK_FREQUENCY
 221                 )
 222             port map(
 223                 ext_clk => ext_clk,
 224                 pll_rst_in => pll_rst,
 225                 pll_clk_out => system_clk,
 226                 pll_locked_out => system_clk_locked
 227                 );
 228
 229         led0 <= soc_rst;
 230         led1 <= pll_rst;
 231         led2 <= not system_clk_locked;
 232         led3 <= '0';
 233         core_alt_reset <= '0';
 234
 235         -- Vivado barfs on those differential signals if left
 236         -- unconnected. So instanciate a diff. buffer and feed
 237         -- it a constant '0'.
 238         dummy_dram_clk: OBUFDS
 239             port map (
 240                 O => ddram_clk_p,
 241                 OB => ddram_clk_n,
 242                 I => ddram_clk_dummy
 243                 );
 244         ddram_clk_dummy <= '0';
 245
 246     end generate;
 247
 248     has_dram: if USE_LITEDRAM generate
 249         signal dram_init_done  : std_ulogic;
 250         signal dram_init_error : std_ulogic;
 251         signal dram_sys_rst    : std_ulogic;
 252     begin
 253
 254         -- Eventually dig out the frequency from the generator
 255         -- but for now, assert it's 100Mhz
 256         assert CLK_FREQUENCY = 100000000;
 257
 258         reset_controller: entity work.soc_reset
 259             generic map(
 260                 RESET_LOW => RESET_LOW,
 261                 PLL_RESET_BITS => 18,
 262                 SOC_RESET_BITS => 1
 263                 )
 264             port map(
 265                 ext_clk => ext_clk,
 266                 pll_clk => system_clk,
 267                 pll_locked_in => '1',
 268                 ext_rst_in => ext_rst,
 269                 pll_rst_out => pll_rst,
 270                 rst_out => open
 271                 );
 272
 273         dram: entity work.litedram_wrapper
 274             generic map(
 275                 DRAM_ABITS => 25,
 276                 DRAM_ALINES => 15,
 277                 DRAM_DLINES => 32,
 278                 DRAM_PORT_WIDTH => 256,
 279                 PAYLOAD_FILE => RAM_INIT_FILE,
 280                 PAYLOAD_SIZE => PAYLOAD_SIZE
 281                 )
 282             port map(
 283                 clk_in          => ext_clk,
 284                 rst             => pll_rst,
 285                 system_clk      => system_clk,
 286                 system_reset    => soc_rst,
 287                 core_alt_reset  => core_alt_reset,
 288                 pll_locked      => system_clk_locked,
 289
 290                 wb_in           => wb_dram_in,
 291                 wb_out          => wb_dram_out,
 292                 wb_ctrl_in      => wb_ext_io_in,
 293                 wb_ctrl_out     => wb_ext_io_out,
 294                 wb_ctrl_is_csr  => wb_ext_is_dram_csr,
 295                 wb_ctrl_is_init => wb_ext_is_dram_init,
 296
 297                 init_done       => dram_init_done,
 298                 init_error      => dram_init_error,
 299
 300                 ddram_a         => ddram_a,
 301                 ddram_ba        => ddram_ba,
 302                 ddram_ras_n     => ddram_ras_n,
 303                 ddram_cas_n     => ddram_cas_n,
 304                 ddram_we_n      => ddram_we_n,
 305                 ddram_cs_n      => ddram_cs_n,
 306                 ddram_dm        => ddram_dm,
 307                 ddram_dq        => ddram_dq,
 308                 ddram_dqs_p     => ddram_dqs_p,
 309                 ddram_dqs_n     => ddram_dqs_n,
 310                 ddram_clk_p     => ddram_clk_p,
 311                 ddram_clk_n     => ddram_clk_n,
 312                 ddram_cke       => ddram_cke,
 313                 ddram_odt       => ddram_odt,
 314                 ddram_reset_n   => ddram_reset_n
 315                 );
 316
 317         led0 <= soc_rst;
 318         led1 <= pll_rst;
 319         led2 <= not dram_init_done or dram_init_error;
 320         led3 <= not dram_init_error; -- Make it blink ?
 321     end generate;
 322 end architecture behaviour;