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[libreriscv.git] / index.mdwn
1 <div class="jumbotron">
2 <h1 class="display-5">Welcome to Libre-SOC</h1>
3 <blockquote>
4 <p>We're building a chip. A fast chip. A safe chip. A trusted chip.</p>
5
6 <p>A chip with lots of peripherals. And a VPU. And a 3D GPU...</p>
7
8 <p>Oh and here, have the <a href="http://git.libre-riscv.org">source code</a>...</p>
9 </blockquote>
10 <hr class="my-4">
11
12 <h2 class="display-5">Why should I care?</h2>
13
14 With LibreSOC, you can take complex algorithms usually intended for
15 power hungry servers with big fat GPUs, and run them on tiny devices
16 like smartwatches, cellphones, and pocket drones without changing your
17 code at all.
18
19 <hr class="my-4">
20
21 <h2 class="display-5">Hasn't Somebody Already Done This?</h2>
22
23 To the best of our knowledge, no. The closest systems would be ARM Cortex
24 devices which currently offer mediocre GPU and OpenCL support. Often
25 times, it is quite diffcult for customers to get their hands on the
26 drivers and install them due to their locked down nature. LibreSOC is
27 providing our own Free/Libre drivers. Easy as 1, 2, 3!
28
29 <hr class="my-4">
30
31 <h2 class="display-5">Does Open Hardware Really Work?</h2>
32 <p>A few names come to mind:</p>
33
34 <ul>
35 <li><a href="https://www.raspberrypi.org">Raspberry Pi</a></li>
36 <li><a href="https://www.arduino.cc">Arduino</a></li>
37 <li><a href="https://www.raptorcs.com">Raptor Computing Systems</a></li>
38 <li><a href="https://www.bitcraze.io">CrazyFlie</a></li>
39 <li><a href="https://www.scopefun.com">ScopeFun</a></li>
40 </ul>
41
42 <p class="lead">
43 <a class="btn btn-primary btn-lg" href="https://libre-soc.org/why_a_libresoc/" role="button">Learn more</a>
44
45 </div>
46
47
48
49 # Our Team
50
51 We are proud of our talented and diverse [team](about_us).
52
53 # Our sponsors
54
55 * [Purism](http://puri.sm) donates to us through [NLNet](nlnet)
56 charitable gifting
57 * [Raptor CS](http://raptorcs.com) has given us access to a powerful
58 18-core 128 GB RAM TALOS II workstation, online.
59
60 # How Can I Help?
61
62 If you would like to fund us, see [[funding]]. We currently have some
63 funding and always appreciate more! If you are a Corporation or an
64 individual you can donate tax-free to NLNet, and they can in turn gift
65 our developers. Contact lkcl@lkcl.net for more information.
66
67 If you want to write code with us (and receive donations from NLNet
68 for doing so), keep reading. If you want to *learn*
69 so that you can write code with us, see below. If there is anything else,
70 just get in touch on the list, there is plenty to do.
71
72 1. First, join the
73 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
74 introduce yourself (people will happily say "hello" back"). Read through
75 [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
76 and the [[charter]], and let everyone know, on the list that you're
77 happy with it and agree to it.
78 2. The next thing you should do is read through the [bugs
79 list](http://bugs.libre-riscv.org) and see if there are any bugs that
80 pique your interest.
81 3. After that, go ahead and take a look at the [git repositories](https://git.libre-riscv.org).
82
83 4. If you plan to do HDL work, you should familiarize yourself with our
84 [[HDL_workflow]].
85 5. We do have funding available (see [[nlnet]]) upon completion of issues -
86 we are also working on procuring more funding which gets the project to
87 nanometre scale tapeout.
88 6. After all this, if you feel that Libre-SOC is a something
89 that you would like to contribute to, add yourself to the
90 [current_members](about_us) page, fill in some information about yourself,
91 and join the mailing list and say hello.
92
93 Also note that you can edit this wiki. You can experiment in the [[Sandbox]].
94
95 ## Quick peek at the code
96
97 Here is an example process of how to play with the soc code:
98
99 <div class="jumbotron">
100 pip3 install virtualenv requests <br />
101 mkdir ~/.virtualenvs && cd ~/.virtualenvs <br />
102 python3 -m venv libresoc <br />
103 source ~/.virtualenvs/bin/activate <br />
104 <br />
105 cd ~; mkdir libresoc; cd libresoc <br />
106 git clone https://git.libre-riscv.org/git/nmutil.git <br />
107 git clone https://git.libre-riscv.org/git/ieee754fpu.git <br />
108 git clone --recursive https://git.libre-riscv.org/git/soc.git <br />
109 <br />
110 cd nmutil; pip3 install -e .; cd .. <br />
111 cd ieee754fpu; pip3 install -e .; cd .. <br />
112 cd soc; pip3 install -e .; cd .. <br />
113 <br />
114 # play with the decoder <br />
115 python3 soc/src/soc/decoder/power_decoder.py <br />
116 # after installing yosys <br />
117 yosys -p "read_ilang decoder.il; show dec31" <br />
118 </div>
119
120 ## How can I learn?
121
122 The whole purpose of this project is to be a learning environment as well
123 as an actual business. If you want to learn how to do ASIC design, with
124 a view to contributing or starting your own ASIC business, start here:
125 [[3d_gpu/tutorial]]. Yes, really: do not let anyone tell you that you
126 can't learn this stuff too.
127
128 Along the way, if you find any [[resources]] or links that you found
129 particularly helpful, please add them to that page so that other people
130 can also benefit (and you have a place to remember them, too).
131
132 ## Needed Skills
133
134 Most labor is currently being applied to developing the GPU portion of
135 the Libre-SOC.
136
137 The highest priority needed at the moment is a c++ engineer to work on
138 a MESA 3D driver. This will begin life similar to SwiftShader however
139 retaining the vectorisation and predication intrinsics as well as hardware
140 accelerated opcodes (all of which SwiftShader lacks)
141
142 Medium to long-term we need HDL engineers. Particularly those familiar
143 with nMigen or just python. Most of the techniques being used require
144 software engineering skills (OO design, polymorphism) than they do more
145 traditional HDL programming skills. Basically if you have experience in 2
146 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
147 design. See [[HDL_workflow]]
148
149 Also, individuals with experience in formal mathematical verification
150 are quite welcome.