index.mdwn

   1 # Welcome to Libre-SOC
   2 (formerly Libre-RISCV)
   3
   4 > We're building a chip. A fast chip. A safe chip. A trusted chip.
   5
   6 > A chip with lots of peripherals. And a VPU.  And a 3D GPU...
   7
   8 > Oh and here, have the [source code](http://git.libre-riscv.org)...
   9
  10 Sounds cool? Learn more about the [why](why_a_libresoc) behind Libre-SOC
  11 and [our mission](The_Mission).
  12
  13 # Our Team
  14
  15 We are proud of our talented and diverse [team](about_us).
  16
  17 # Our sponsors
  18
  19 * [Purism](http://puri.sm) donates to us through [NLNet](nlnet)
  20   charitable gifting
  21 * [Raptor CS](http://raptorcs.com) has given us access to a powerful
  22   18-core 128 GB RAM TALOS II workstation, online.
  23
  24 # How Can I Help?
  25
  26 If you would like to fund us, see [[funding]]. We currently have some
  27 funding and always appreciate more!  If you are a Corporation or an
  28 individual you can donate tax-free to NLNet, and they can in turn gift
  29 our developers.  Contact lkcl@lkcl.net for more information.
  30
  31 If you want to write code with us, keep reading.  If you want to *learn* so that you can write code with us, see below.  If there is anything else, just get in touch on the list, there is plenty to do.
  32
  33 1. First, join the
  34 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
  35 introduce yourself (people will happily say "hello" back"). Read through
  36 [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
  37 and the [[charter]], and let everyone know, on the list that you're
  38 happy with it and agree to it.
  39 2. The next thing you should do is read through the [bugs
  40 list](http://bugs.libre-riscv.org) and see if there are any bugs that
  41 pique your interest.
  42 3. After that, go ahead and take a look at the resources section below.
  43 Try and clone a repository with
  44 ``git clone https://git.libre-riscv.org/git/repositoryname.git``
  45 4. If you plan to do HDL work, you should familiarize yourself with our
  46    [[HDL_workflow]].
  47 5. We do have funding available (see [[nlnet]]) upon completion of issues -
  48 we are also working on procuring more funding which gets the project to
  49 nanometre scale tapeout.
  50 6. After all this, if you feel that Libre-SOC is a something that
  51 you would like to contribute to, add yourself to the [current_members](about_us)
  52 page, fill in some information about yourself, and join the mailing list
  53 and say hello.
  54
  55 Also note that you can edit this wiki.  You can experiment in the [[Sandbox]].
  56
  57 ## How can I learn?
  58
  59 The whole purpose of this project is to be a learning environment as well as an actual business.  If you want to learn how to do ASIC design, with a view to contributing or starting your own ASIC business, start here: [[3d_gpu/tutorial]]. Yes, really: do not let anyone tell you that you can't learn this stuff too.
  60
  61 Along the way, if you find any [[resources]] or links that you found particularly helpful, please add them to that page so that other people can also benefit (and you have a place to remember them, too).
  62
  63 ## Needed Skills
  64
  65 Most labor is currently being applied to developing the GPU portion of
  66 the Libre-SOC.
  67
  68 The highest priority needed at the moment is a c++ engineer to work on
  69 a MESA 3D driver. This will begin life similar to SwiftShader however
  70 retaining the vectorisation and predication intrinsics as well as hardware
  71 accelerated opcodes (all of which SwiftShader lacks)
  72
  73 Medium to long-term we need HDL engineers. Particularly those familiar
  74 with nMigen or just python.  Most of the techniques being used require
  75 software engineering skills (OO design, polymorphism) than they do more
  76 traditional HDL programming skills. Basically if you have experience in 2
  77 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
  78 design. See [[HDL_workflow]]
  79
  80 Also, individuals with experience in formal mathematical verification
  81 are quite welcome.
  82