isa_conflict_resolution/mvendor_march_mimplid.mdwn

   1 # mvendorid/marchid/mimplid (mvendorid/marchid MRO, mimplid WARL)<a name="mvendor_marchid_mimplid"></a>
   2
   3 This proposal explores the possibility of adding a "mimplid" (or isamux) CSR
   4 that acts as an extra bit of state that goes directly into instruction decoding.
   5 It would be analogous to extending every single RISC-V instruction by a few bits
   6 so as to guarantee that no conflicts may occur in either custom extensions or
   7 future revisions of the RISC-V Standard, as well as permitting processors
   8 to execute (rather than JIT decode) completely foreign architectures.
   9
  10 Implementors register (mvendorid-marchid-mimpl) tuples with the FSF
  11 gcc and binutils teams, effectively making the FSF the de-facto atomic
  12 arbiter responsible for maintaining the world-wide unique encoding
  13 database as part of the gcc and binutils codebase.
  14
  15 Conflicting custom extensions thus become world-wide globally unique
  16 such that assembly writers, gcc and binutils may have a high to 100%
  17 degree of confidence that a given binary will not need recompiling from
  18 source, if transferred from one architecture to another (that has the
  19 exact same set of extensions).
  20
  21 # Ideas discussed so far
  22
  23 ## One hart, one ISA encoding
  24
  25 This idea is quite straightforward: on any given multi-core processor
  26 it can have multiple mvendorid-marchid-mimplid tuples, where each core
  27 (hart) has *one* and *only* one tuple.  Thus, running different
  28 encodings is a simple matter of selecting the correct core.
  29
  30 There are a couple of issues with this approach:
  31
  32 * Single-core implementations are not possible.
  33 * Multi-core implementations are guaranteed, for high workloads,
  34   to have "incompatible" cores sitting idle whilst "compatible"
  35   cores are overloaded.
  36
  37 Aside from those limitations it is a workable and valid proposal that has the
  38 potential to meet the requirements, that may turn out to be a legitimate
  39 and simple and easy to implement subset of other ideas outlined in this
  40 document.
  41
  42 ## Every hart, multiple ISA encodings, mimpl unchanged on traps
  43
  44 This idea allows every hart (core) to have the ability to select
  45 any one of multiple ISA encodings, by setting mimpl *in U-mode*.
  46
  47 ## Every hart, multiple ISA encodings, mimpl set to "default" on traps
  48
  49 ## Every hart, multiple ISA encodings, mimpl set to "supervisor-selectable"
  50