isa_conflict_resolution/mvendor_march_mimplid.mdwn

   1 # mvendorid/marchid/mimplid (mvendorid/marchid MRO, mimplid WARL)<a name="mvendor_marchid_mimplid"></a>
   2
   3 This proposal explores the possibility of adding a "mimplid" (or isamux) CSR
   4 that acts as an extra bit of state that goes directly into instruction decoding.
   5 It would be analogous to extending every single RISC-V instruction by a few bits
   6 so as to guarantee that no conflicts may occur in either custom extensions or
   7 future revisions of the RISC-V Standard, as well as permitting processors
   8 to execute (rather than JIT decode) completely foreign architectures.
   9
  10 Implementors register (mvendorid-marchid-mimpl) tuples with the FSF
  11 gcc and binutils teams, effectively making the FSF the de-facto atomic
  12 arbiter responsible for maintaining the world-wide unique encoding
  13 database as part of the gcc and binutils codebase.
  14
  15 Conflicting custom extensions thus become world-wide globally unique
  16 such that assembly writers, gcc and binutils may have a high to 100%
  17 degree of confidence that a given binary will not need recompiling from
  18 source, if transferred from one architecture to another (that has the
  19 exact same set of extensions).
  20
  21 # Ideas discussed so far
  22
  23 ## One hart, one ISA encoding
  24
  25 This idea is quite straightforward: on any given multi-core processor
  26 it can have multiple mvendorid-marchid-mimplid tuples, where each core
  27 (hart) has *one* and *only* one tuple.  Thus, running different
  28 encodings is a simple matter of selecting the correct core.
  29
  30 clarification from jacob:
  31
  32 > it solves the problem of one implementation needing to implement
  33 > conflicting extensions, with some limitations, specifically that each of
  34 > the conflicting extensions must be used in separate threads.  The Rocket
  35 > RoCC coprocessor interface, in a multi-tile SoC where different tiles
  36 > have different coprocessors, provides a working example of this model.
  37 > The overall system has both of two conflicting coprocessors.
  38
  39 There are a couple of issues with this approach:
  40
  41 * Single-core (single hart) implementations are not possible.
  42 * Multi-core implementations are guaranteed, for high workloads,
  43   to have "incompatible" cores sitting idle whilst "compatible"
  44   cores are overloaded.
  45
  46 Aside from those limitations it is a workable and valid proposal that has the
  47 potential to meet the requirements, that may turn out to be a legitimate
  48 and simple and easy to implement subset of other ideas outlined in this
  49 document.
  50
  51 ## Every hart, multiple ISA encodings, mimpl unchanged on traps
  52
  53 This idea allows every hart (core) to have the ability to select
  54 any one of multiple ISA encodings, by setting mimpl *in U-mode*.
  55
  56 > I agree.. complete renumbering is a huge overhead. Guy's solution avoids
  57 > that overhead and provides a fast-switching mechanism.  We had already
  58 > identified what happens on traps, flushes, caches, etc. Would prefer if
  59 > we could review/critique that proposal.
  60 >
  61 > If someone wants to re-number the entire custom ISA even then Guy's
  62 > solution will stand.  Plus, in the heterogenous envrionemt, considering
  63 > each hart/core has its own marcselect(mutable csr), the M mode (or
  64 > user/supervisor) can simply choose to enable that hart/core by writing
  65 > to the marchselect CSR.
  66 >
  67 > For compliance, yes we will need Jacob's idea of having a global database
  68 > somewhere. Also, I believe that the compliance will check only if the
  69 > core is RISC-V compliant and not worry about any other extensions present
  70 > or not.
  71 >
  72 > By adding a new mutable csr in the MRW region even existing
  73 > implementations will be compliant since accessing this CSR in current
  74 > implementations would just trap.
  75
  76 ## Every hart, multiple ISA encodings, mimpl set to "default" on traps
  77
  78 ## Every hart, multiple ISA encodings, mimpl set to "supervisor-selectable"
  79