lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7
   8 # Status tracking
   9
  10 move things along from one stage to the next
  11
  12 ## Currently working on
  13
  14  - Project Management
  15  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  16  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documrntation
  20    - EUR
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  22    - EUR
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  32  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  33  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  36    - shared with cole
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  38    - EUR 50, shared with samuel 10%
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  43    - EUR 50, shared with samuel (EUR 350)
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  50    - EUR 200
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  57    - donated
  58    - parent #198
  59    - EUR 200
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  61   - MultiCompUnit (and Function Units) proof
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  63   - donated
  64   - parent #195
  65
  66 ## Completed but not yet submitted:
  67
  68  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
  69   - Project 2019-10-043 06dec2020 wishbone
  70   - EUR 0 (TBD)
  71
  72 ### Project 2019-10-029 14mar2020 coriolis2
  73
  74  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
  75    - (total EUR 100 shared 50% with staf)
  76    - EUR 50 lkcl
  77  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
  78    - (total EUR 1500 shared 50% with LIP6)
  79    - EUR 750 lkcl
  80  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  81    - (total EUR 400 shared 75% with LIP6)
  82    - EUR 300 lkcl
  83
  84 ### Project 2019-02-012 06dec2020 Core
  85
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
  87    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
  88  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
  89    - EUR 750 donated
  90  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
  91    - EUR 1500
  92
  93 ### Project 2019-10-043 06dec2020 wishbone
  94
  95  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
  96    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
  98    - EUR 200
  99  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 100    - EUR 100
 101  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 102    - EUR 200
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 104    - EUR 100
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 106    - EUR 200
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 108    - EUR 450
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 110    - EUR 100
 111  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 112    - EUR 200 donated
 113  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 114    - EUR 250 (share with cole)
 115
 116 ### Project 2019-10-032 06dec2020 proofs
 117
 118  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 119    - parent #195
 120    - EUR 400 donated
 121  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 122    - parent #195
 123    - EUR 300 donated
 124  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 125    - EUR 400 donated
 126    - parent #195
 127  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 128    - EUR 400 donated
 129    - parent #195
 130
 131 ## Submitted for NLNet RFP
 132
 133 submitted but not confirmed paid:
 134
 135 ### Project 2019-02-012 04sep2020 Core
 136
 137  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 138    - EUR 2000 total, shared with florent.  EUR 1200
 139
 140 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 141
 142 ## Paid
 143
 144 donation from NLNet confirmed received:
 145
 146 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 147
 148  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 149     - EUR 2000, python POWER9 simulator
 150     - Shared 50% with [[mnolan]], EUR 1000
 151  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 152     - EUR 250, functions needed for simulator
 153     - Shared 20% with [[mnolan]], EUR 50
 154
 155 ### proofs 2019-10-032
 156
 157  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 158    - EUR 500 shared 20% samuel, EUR 100
 159  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 160    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 161  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 162    - EUR 400 shared 25% [[mnolan]] EUR 100
 163  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 164    - EUR 150
 165
 166 ### wishbone 2019-10-043
 167
 168  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 169    - EUR 500
 170  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 171     - EUR 300
 172  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 173     - EUR 250
 174  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 175    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 176  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 177    - EUR 300
 178  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 179    - EUR 400, 50% shared [[programmerjake]] EUR 200
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 181    - EUR 750, 33% shared [[programmerjake]] EUR 250
 182  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 183    - EUR 200 50% shared, cole, EUR 100
 184  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 185    - EUR 200
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 187    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 189    - EUR 150
 190  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 191    - EUR 400 shared 50% [[mnolan]] EUR 200
 192  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 193    - EUR 250 shared 40% [[mnolan]] EUR 100
 194  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 195    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 196  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 197    - EUR 300 shared 50% [[mnolan]] EUR 150
 198  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 199    - EUR 750
 200  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 201   - EUR 100
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 203   - EUR 100
 204  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 205    - EUR 100
 206  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 207    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 208
 209 ### Project 2019-02-012 28-apr-2020
 210
 211  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 212    - 6600 scoreboard multi-read/write
 213    - EUR 600
 214  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 215    - Partitioned equals and greater than comparison
 216    - Shared 50% with [[mnolan]]
 217    - EUR 200 (each)
 218  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 219    - partitioned scalar/vector shift
 220    - Shared 50% with [[lkcl]]
 221    - EUR 350 (each)
 222
 223 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 224
 225  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 226     - auto-parser of POWER9
 227     - Shared 50% with [[mnolan]]
 228     - EUR 500 (each)
 229
 230 ### Project 2019-10-029 Date 14mar2020
 231
 232 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 233   - EUR 1200
 234
 235 ### Project 2019-02-012 Date 12mar2020
 236
 237 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 238 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 239 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 240 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 241
 242 ### Project 2019-02-012 Date 28jan2020
 243
 244 * admin tasks
 245 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 246