lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7
   8 # Status tracking
   9
  10 move things along from one stage to the next
  11
  12 ## Currently working on
  13
  14  - Project Management
  15  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  16  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  17  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documrntation
  21    - EUR
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  23    - EUR
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  33  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  34  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  37    - shared with cole
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  39    - EUR 50, shared with samuel 10%
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  44    - EUR 50, shared with samuel (EUR 350)
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  51    - EUR 200
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  58    - donated
  59    - parent #198
  60    - EUR 200
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  62   - MultiCompUnit (and Function Units) proof
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  64   - donated
  65   - parent #195
  66
  67 ## Completed but not yet submitted:
  68
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
  70  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
  71   - Project 2019-10-043 06dec2020 wishbone
  72   - EUR 0 (TBD)
  73
  74 ### Project 2019-10-029 14mar2020 coriolis2
  75
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
  77    - (total EUR 100 shared 50% with staf)
  78    - EUR 50 lkcl
  79  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
  80    - (total EUR 1500 shared 50% with LIP6)
  81    - EUR 750 lkcl
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  83    - (total EUR 400 shared 75% with LIP6)
  84    - EUR 300 lkcl
  85
  86 ### Project 2019-02-012 06dec2020 Core
  87
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
  89    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
  90  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
  91    - EUR 750 donated
  92  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
  93    - EUR 1500
  94
  95 ### Project 2019-10-043 06dec2020 wishbone
  96
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
  98    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
  99  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 100    - EUR 200
 101  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 102    - EUR 100
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 104    - EUR 200
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 106    - EUR 100
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 108    - EUR 200
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 110    - EUR 450
 111  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 112    - EUR 100
 113  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 114    - EUR 200 donated
 115  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 116    - EUR 250 (share with cole)
 117
 118 ### Project 2019-10-032 06dec2020 proofs
 119
 120  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 121    - parent #195
 122    - EUR 400 donated
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 124    - parent #195
 125    - EUR 300 donated
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 127    - EUR 400 donated
 128    - parent #195
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 130    - EUR 400 donated
 131    - parent #195
 132
 133 ## Submitted for NLNet RFP
 134
 135 submitted but not confirmed paid:
 136
 137 ### Project 2019-02-012 04sep2020 Core
 138
 139  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 140    - EUR 2000 total, shared with florent.  EUR 1200
 141
 142 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 143
 144 ## Paid
 145
 146 donation from NLNet confirmed received:
 147
 148 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 149
 150  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 151     - EUR 2000, python POWER9 simulator
 152     - Shared 50% with [[mnolan]], EUR 1000
 153  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 154     - EUR 250, functions needed for simulator
 155     - Shared 20% with [[mnolan]], EUR 50
 156
 157 ### proofs 2019-10-032
 158
 159  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 160    - EUR 500 shared 20% samuel, EUR 100
 161  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 162    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 163  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 164    - EUR 400 shared 25% [[mnolan]] EUR 100
 165  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 166    - EUR 150
 167
 168 ### wishbone 2019-10-043
 169
 170  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 171    - EUR 500
 172  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 173     - EUR 300
 174  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 175     - EUR 250
 176  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 177    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 178  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 179    - EUR 300
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 181    - EUR 400, 50% shared [[programmerjake]] EUR 200
 182  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 183    - EUR 750, 33% shared [[programmerjake]] EUR 250
 184  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 185    - EUR 200 50% shared, cole, EUR 100
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 187    - EUR 200
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 189    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 190  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 191    - EUR 150
 192  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 193    - EUR 400 shared 50% [[mnolan]] EUR 200
 194  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 195    - EUR 250 shared 40% [[mnolan]] EUR 100
 196  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 197    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 198  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 199    - EUR 300 shared 50% [[mnolan]] EUR 150
 200  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 201    - EUR 750
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 203   - EUR 100
 204  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 205   - EUR 100
 206  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 207    - EUR 100
 208  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 209    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 210
 211 ### Project 2019-02-012 28-apr-2020
 212
 213  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 214    - 6600 scoreboard multi-read/write
 215    - EUR 600
 216  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 217    - Partitioned equals and greater than comparison
 218    - Shared 50% with [[mnolan]]
 219    - EUR 200 (each)
 220  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 221    - partitioned scalar/vector shift
 222    - Shared 50% with [[lkcl]]
 223    - EUR 350 (each)
 224
 225 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 226
 227  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 228     - auto-parser of POWER9
 229     - Shared 50% with [[mnolan]]
 230     - EUR 500 (each)
 231
 232 ### Project 2019-10-029 Date 14mar2020
 233
 234 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 235   - EUR 1200
 236
 237 ### Project 2019-02-012 Date 12mar2020
 238
 239 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 240 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 241 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 242 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 243
 244 ### Project 2019-02-012 Date 28jan2020
 245
 246 * admin tasks
 247 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 248