(no commit message)
[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
17 - https://bugs.libre-soc.org/show_bug.cgi?id=575
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
21 - EUR
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
30 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
31 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
34 - shared with cole
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
36 - EUR 50, shared with samuel 10%
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
41 - EUR 50, shared with samuel (EUR 350)
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
48 - EUR 200
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
55 - donated
56 - parent #198
57 - EUR 200
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
59 - MultiCompUnit (and Function Units) proof
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
61 - donated
62 - parent #195
63
64 ## Completed but not yet submitted:
65
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
67 - EUR 150
68 - donated
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
70 - EUR 200
71 - donated
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
73 - EUR 150
74 - donated
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
76 - EUR 200
77 - donated
78 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
79 - EUR 700
80 - (lip6.fr donated)
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
82 - (total EUR 400 25% donated by LIP6)
83 - EUR 100 lkcl
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
85 - EUR 900
86 - shared with [[lxo]]
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
88 - EUR 1100
89 - shared with lauri, jacob
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
91 - EUR 1250
92 - Shared 50% with Staf
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
94 - EUR 300
95 - Shared with Staf, cole
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
97 - EUR 450
98 - Shared with Staf
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
101 - EUR 3000
102 - shared with Staf 50%
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
104 - Project 2019-10-043 06dec2020 wishbone
105 - EUR (TBD)
106
107 ### Project 2019-10-029 14mar2020 coriolis2
108
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
110 - (total EUR 100 shared 50% with staf)
111 - EUR 50 lkcl
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
113 - (total EUR 1500 shared 50% with LIP6)
114 - EUR 750 lkcl
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
116 - (total EUR 400 shared 75% with LIP6)
117 - EUR 300 lkcl
118
119 ### Project 2019-02-012 06dec2020 Core
120
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
122 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
123 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
124 - EUR 750 donated
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
126 - EUR 1500
127
128 ### Project 2019-10-043 06dec2020 wishbone
129
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
131 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
133 - EUR 200
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
135 - EUR 100
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
137 - EUR 200
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
139 - EUR 100
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
141 - EUR 200
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
143 - EUR 450
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
145 - EUR 100
146 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
147 - EUR 200 donated
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
149 - EUR 250 (share with cole)
150
151 ### Project 2019-10-032 06dec2020 proofs
152
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
154 - parent #195
155 - EUR 400 donated
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
157 - parent #195
158 - EUR 300 donated
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
160 - EUR 400 donated
161 - parent #195
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
163 - EUR 400 donated
164 - parent #195
165
166 ## Submitted for NLNet RFP
167
168 submitted but not confirmed paid:
169
170 ### Project 2019-02-012 04sep2020 Core
171
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
173 - EUR 2000 total, shared with florent. EUR 1200
174
175 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
176
177 ## Paid
178
179 donation from NLNet confirmed received:
180
181 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
182
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
184 - EUR 2000, python POWER9 simulator
185 - Shared 50% with [[mnolan]], EUR 1000
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
187 - EUR 250, functions needed for simulator
188 - Shared 20% with [[mnolan]], EUR 50
189
190 ### proofs 2019-10-032
191
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
193 - EUR 500 shared 20% samuel, EUR 100
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
195 - EUR 300 shared 1/6 [[mnolan]] EUR 50
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
197 - EUR 400 shared 25% [[mnolan]] EUR 100
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
199 - EUR 150
200
201 ### wishbone 2019-10-043
202
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
204 - EUR 500
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
206 - EUR 300
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
208 - EUR 250
209 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
210 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
212 - EUR 300
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
214 - EUR 400, 50% shared [[programmerjake]] EUR 200
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
216 - EUR 750, 33% shared [[programmerjake]] EUR 250
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
218 - EUR 200 50% shared, cole, EUR 100
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
220 - EUR 200
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
222 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
224 - EUR 150
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
226 - EUR 400 shared 50% [[mnolan]] EUR 200
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
228 - EUR 250 shared 40% [[mnolan]] EUR 100
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
230 - EUR 300 shared 1/3 [[mnolan]] EUR 100
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
232 - EUR 300 shared 50% [[mnolan]] EUR 150
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
234 - EUR 750
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
236 - EUR 100
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
238 - EUR 100
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
240 - EUR 100
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
242 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
243
244 ### Project 2019-02-012 28-apr-2020
245
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
247 - 6600 scoreboard multi-read/write
248 - EUR 600
249 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
250 - Partitioned equals and greater than comparison
251 - Shared 50% with [[mnolan]]
252 - EUR 200 (each)
253 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
254 - partitioned scalar/vector shift
255 - Shared 50% with [[lkcl]]
256 - EUR 350 (each)
257
258 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
259
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
261 - auto-parser of POWER9
262 - Shared 50% with [[mnolan]]
263 - EUR 500 (each)
264
265 ### Project 2019-10-029 Date 14mar2020
266
267 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
268 - EUR 1200
269
270 ### Project 2019-02-012 Date 12mar2020
271
272 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
273 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
274 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
275 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
276
277 ### Project 2019-02-012 Date 28jan2020
278
279 * admin tasks
280 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
281