1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
45 - https://bugs.libre-soc.org/show_bug.cgi?id=575
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
54 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
55 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
60 - EUR 50, shared with samuel 10%
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
65 - EUR 50, shared with samuel (EUR 350)
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
78 - MultiCompUnit (and Function Units) proof
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
84 ## Completed but not yet submitted:
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
91 * EUR 1500 (shared with [[tplaten]])
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
93 * EUR 1500 (shared with [[tplaten]])
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
95 * EUR 1000 (shared with [[tplaten]])
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
97 * EUR 500 (shared with [[programmerjake]])
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
99 * EUR 400 (shared with [[programmerjake]])
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
105 - EUR 800 shared with [[klehman]]
106 - EUR 800 shared with [[lkcl]]
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
133 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
137 - (total EUR 400 25% donated by LIP6)
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
141 - shared with [[lxo]]
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
144 - shared with lauri, jacob
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
147 - Shared 50% with Staf
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
150 - Shared with Staf, cole
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
156 - Project 2019-10-043 06dec2020 wishbone
159 ### Project 2019-10-029 14mar2020 coriolis2
161 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
162 - (total EUR 100 shared 50% with staf)
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
165 - (total EUR 1500 shared 50% with LIP6)
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
168 - (total EUR 400 shared 75% with LIP6)
171 ### Project 2019-02-012 06dec2020 Core
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
174 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
175 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
180 ### Project 2019-10-043 06dec2020 wishbone
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
183 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
198 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
201 - EUR 250 (share with cole)
203 ### Project 2019-10-032 06dec2020 proofs
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
218 ## Submitted for NLNet RFP
220 submitted 2021-dec-09 but not confirmed paid
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
224 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
229 - EUR 800 shared between:
231 - EUR 300 [[tplaten]]
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
233 - EUR 5500 shared between:
236 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
241 - EUR 500 shared between:
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
248 ### Project 2019-02-012 04sep2020 Core
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
251 - EUR 2000 total, shared with florent. EUR 1200
253 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
257 donation from NLNet confirmed received:
259 ### coriolis2 2021-apr-04
261 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
263 - shared with Staf 50%
265 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
268 - EUR 2000, python POWER9 simulator
269 - Shared 50% with [[mnolan]], EUR 1000
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
271 - EUR 250, functions needed for simulator
272 - Shared 20% with [[mnolan]], EUR 50
274 ### proofs 2019-10-032
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
277 - EUR 500 shared 20% samuel, EUR 100
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
279 - EUR 300 shared 1/6 [[mnolan]] EUR 50
280 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
281 - EUR 400 shared 25% [[mnolan]] EUR 100
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
285 ### wishbone 2019-10-043
287 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
289 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
291 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
293 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
294 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
298 - EUR 400, 50% shared [[programmerjake]] EUR 200
299 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
300 - EUR 750, 33% shared [[programmerjake]] EUR 250
301 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
302 - EUR 200 50% shared, cole, EUR 100
303 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
306 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
310 - EUR 400 shared 50% [[mnolan]] EUR 200
311 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
312 - EUR 250 shared 40% [[mnolan]] EUR 100
313 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
314 - EUR 300 shared 1/3 [[mnolan]] EUR 100
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
316 - EUR 300 shared 50% [[mnolan]] EUR 150
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
326 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
328 ### Project 2019-02-012 28-apr-2020
330 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
331 - 6600 scoreboard multi-read/write
333 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
334 - Partitioned equals and greater than comparison
335 - Shared 50% with [[mnolan]]
337 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
338 - partitioned scalar/vector shift
339 - Shared 50% with [[lkcl]]
342 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
344 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
345 - auto-parser of POWER9
346 - Shared 50% with [[mnolan]]
349 ### Project 2019-10-029 Date 14mar2020
351 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
354 ### Project 2019-02-012 Date 12mar2020
356 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
357 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
358 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
359 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
361 ### Project 2019-02-012 Date 28jan2020
364 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>