1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
10 move things along from one stage to the next
12 ## Currently working on
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
17 - https://bugs.libre-soc.org/show_bug.cgi?id=575
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
30 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
31 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
36 - EUR 50, shared with samuel 10%
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
41 - EUR 50, shared with samuel (EUR 350)
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
59 - MultiCompUnit (and Function Units) proof
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
64 ## Completed but not yet submitted:
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
71 - shared with lauri, jacob
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
74 - Shared 50% with Staf
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
77 - Shared with Staf, cole
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
84 - shared with Staf 50%
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
86 - Project 2019-10-043 06dec2020 wishbone
89 ### Project 2019-10-029 14mar2020 coriolis2
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
92 - (total EUR 100 shared 50% with staf)
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
95 - (total EUR 1500 shared 50% with LIP6)
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
98 - (total EUR 400 shared 75% with LIP6)
101 ### Project 2019-02-012 06dec2020 Core
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
104 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
105 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
110 ### Project 2019-10-043 06dec2020 wishbone
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
113 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
128 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
131 - EUR 250 (share with cole)
133 ### Project 2019-10-032 06dec2020 proofs
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
148 ## Submitted for NLNet RFP
150 submitted but not confirmed paid:
152 ### Project 2019-02-012 04sep2020 Core
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
155 - EUR 2000 total, shared with florent. EUR 1200
157 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
161 donation from NLNet confirmed received:
163 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
166 - EUR 2000, python POWER9 simulator
167 - Shared 50% with [[mnolan]], EUR 1000
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
169 - EUR 250, functions needed for simulator
170 - Shared 20% with [[mnolan]], EUR 50
172 ### proofs 2019-10-032
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
175 - EUR 500 shared 20% samuel, EUR 100
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
177 - EUR 300 shared 1/6 [[mnolan]] EUR 50
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
179 - EUR 400 shared 25% [[mnolan]] EUR 100
180 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
183 ### wishbone 2019-10-043
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
191 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
192 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
196 - EUR 400, 50% shared [[programmerjake]] EUR 200
197 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
198 - EUR 750, 33% shared [[programmerjake]] EUR 250
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
200 - EUR 200 50% shared, cole, EUR 100
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
204 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
208 - EUR 400 shared 50% [[mnolan]] EUR 200
209 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
210 - EUR 250 shared 40% [[mnolan]] EUR 100
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
212 - EUR 300 shared 1/3 [[mnolan]] EUR 100
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
214 - EUR 300 shared 50% [[mnolan]] EUR 150
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
224 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
226 ### Project 2019-02-012 28-apr-2020
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
229 - 6600 scoreboard multi-read/write
231 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
232 - Partitioned equals and greater than comparison
233 - Shared 50% with [[mnolan]]
235 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
236 - partitioned scalar/vector shift
237 - Shared 50% with [[lkcl]]
240 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
243 - auto-parser of POWER9
244 - Shared 50% with [[mnolan]]
247 ### Project 2019-10-029 Date 14mar2020
249 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
252 ### Project 2019-02-012 Date 12mar2020
254 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
255 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
256 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
257 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
259 ### Project 2019-02-012 Date 28jan2020
262 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>