lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
  20   - EUR 150
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
  22   - EUR 150
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
  26    - EUR 250
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
  28    - EUR 1250
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  38  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  42    - EUR
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  47  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  48  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  51    - shared with cole
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  53    - EUR 50, shared with samuel 10%
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  55
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  58    - EUR 50, shared with samuel (EUR 350)
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  64    - EUR 200
  65  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  66  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  67    - donated
  68    - parent #198
  69    - EUR 200
  70  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  71   - MultiCompUnit (and Function Units) proof
  72  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  73   - donated
  74   - parent #195
  75  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  76
  77 ## Completed but not yet submitted:
  78
  79 TO SORT
  80
  81 28feb2022
  82
  83  - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
  84    * EUR 1500 (shared with [[tplaten]])
  85  - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
  86    * EUR 1500 (shared with [[tplaten]])
  87  - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
  88    * EUR 1000 (shared with [[tplaten]])
  89  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
  90    * EUR 500 (shared with [[programmerjake]])
  91  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  92    * EUR 400 (shared with [[programmerjake]])
  93
  94 before that
  95
  96  - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
  97    - EUR 1600
  98    - EUR 800 shared with [[klehman]]
  99    - EUR 800 shared with [[lkcl]]
 100  - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
 101    - EUR 800
 102  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
 104  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
 106    - EUR 500
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
 108  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
 111  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
 112
 113
 114  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 115    - EUR 150
 116    - donated
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 118    - EUR 200
 119    - donated
 120  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 121    - EUR 150
 122    - donated
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 124    - EUR 200
 125    - donated
 126  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
 127    - EUR 700
 128    - (lip6.fr donated)
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 130    - (total EUR 400 25% donated by LIP6)
 131    - EUR 100 lkcl
 132  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 133    - EUR 900
 134    - shared with [[lxo]]
 135  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 136    - EUR 1100
 137    - shared with lauri, jacob
 138  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 139    - EUR 1250
 140    - Shared 50% with Staf
 141  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 142    - EUR 300
 143    - Shared with Staf, cole
 144  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 145    - EUR 450
 146    - Shared with Staf
 147  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 148  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 149    - Project 2019-10-043 06dec2020 wishbone
 150    - EUR (TBD)
 151
 152 ### Project 2019-10-029 14mar2020 coriolis2
 153
 154  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 155    - (total EUR 100 shared 50% with staf)
 156    - EUR 50 lkcl
 157  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 158    - (total EUR 1500 shared 50% with LIP6)
 159    - EUR 750 lkcl
 160  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 161    - (total EUR 400 shared 75% with LIP6)
 162    - EUR 300 lkcl
 163
 164 ### Project 2019-02-012 06dec2020 Core
 165
 166  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 167    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 168  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 169    - EUR 750 donated
 170  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 171    - EUR 1500
 172
 173 ### Project 2019-10-043 06dec2020 wishbone
 174
 175  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 176    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 177  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 178    - EUR 200
 179  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 180    - EUR 100
 181  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 182    - EUR 200
 183  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 184    - EUR 100
 185  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 186    - EUR 200
 187  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 188    - EUR 450
 189  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 190    - EUR 100
 191  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 192    - EUR 200 donated
 193  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 194    - EUR 250 (share with cole)
 195
 196 ### Project 2019-10-032 06dec2020 proofs
 197
 198  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 199    - parent #195
 200    - EUR 400 donated
 201  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 202    - parent #195
 203    - EUR 300 donated
 204  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 205    - EUR 400 donated
 206    - parent #195
 207  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 208    - EUR 400 donated
 209    - parent #195
 210
 211 ## Submitted for NLNet RFP
 212
 213 submitted 2021-dec-09 but not confirmed paid
 214
 215  - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
 216    - EUR 300
 217  - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
 218    - EUR 250
 219  - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
 220  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
 221  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
 222    - EUR 800 shared between:
 223    - EUR 500 [[lkcl]]
 224    - EUR 300 [[tplaten]]
 225  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
 226    - EUR 5500 shared between:
 227    - EUR 3850 lkcl
 228    - EUR 1650 Others
 229  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
 230    - EUR 1600
 231  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
 232    - EUR 600
 233  - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
 234    - EUR 500 shared between:
 235    - EUR 100 [[lkcl]]
 236    - EUR 325 dmitry
 237    - EUR 75 maciej
 238  - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
 239
 240
 241 ### Project 2019-02-012 04sep2020 Core
 242
 243  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 244    - EUR 2000 total, shared with florent.  EUR 1200
 245
 246 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 247
 248 ## Paid
 249
 250 donation from NLNet confirmed received:
 251
 252 ### coriolis2 2021-apr-04
 253
 254  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 255    - EUR 3000
 256    - shared with Staf 50%
 257
 258 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 259
 260  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 261     - EUR 2000, python POWER9 simulator
 262     - Shared 50% with [[mnolan]], EUR 1000
 263  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 264     - EUR 250, functions needed for simulator
 265     - Shared 20% with [[mnolan]], EUR 50
 266
 267 ### proofs 2019-10-032
 268
 269  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 270    - EUR 500 shared 20% samuel, EUR 100
 271  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 272    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 273  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 274    - EUR 400 shared 25% [[mnolan]] EUR 100
 275  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 276    - EUR 150
 277
 278 ### wishbone 2019-10-043
 279
 280  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 281    - EUR 500
 282  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 283     - EUR 300
 284  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 285     - EUR 250
 286  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 287    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 288  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 289    - EUR 300
 290  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 291    - EUR 400, 50% shared [[programmerjake]] EUR 200
 292  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 293    - EUR 750, 33% shared [[programmerjake]] EUR 250
 294  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 295    - EUR 200 50% shared, cole, EUR 100
 296  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 297    - EUR 200
 298  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 299    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 300  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 301    - EUR 150
 302  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 303    - EUR 400 shared 50% [[mnolan]] EUR 200
 304  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 305    - EUR 250 shared 40% [[mnolan]] EUR 100
 306  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 307    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 308  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 309    - EUR 300 shared 50% [[mnolan]] EUR 150
 310  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 311    - EUR 750
 312  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 313   - EUR 100
 314  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 315   - EUR 100
 316  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 317    - EUR 100
 318  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 319    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 320
 321 ### Project 2019-02-012 28-apr-2020
 322
 323  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 324    - 6600 scoreboard multi-read/write
 325    - EUR 600
 326  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 327    - Partitioned equals and greater than comparison
 328    - Shared 50% with [[mnolan]]
 329    - EUR 200 (each)
 330  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 331    - partitioned scalar/vector shift
 332    - Shared 50% with [[lkcl]]
 333    - EUR 350 (each)
 334
 335 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 336
 337  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 338     - auto-parser of POWER9
 339     - Shared 50% with [[mnolan]]
 340     - EUR 500 (each)
 341
 342 ### Project 2019-10-029 Date 14mar2020
 343
 344 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 345   - EUR 1200
 346
 347 ### Project 2019-02-012 Date 12mar2020
 348
 349 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 350 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 351 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 352 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 353
 354 ### Project 2019-02-012 Date 28jan2020
 355
 356 * admin tasks
 357 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 358