lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7
   8 # Status tracking
   9
  10 move things along from one stage to the next
  11
  12 ## Currently working on
  13
  14  - Project Management
  15  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  16  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  17  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documrntation
  21    - EUR
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  23    - EUR
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  33  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  34  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  37    - shared with cole
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  39    - EUR 50, shared with samuel 10%
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  44    - EUR 50, shared with samuel (EUR 350)
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  51    - EUR 200
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  58    - donated
  59    - parent #198
  60    - EUR 200
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  62   - MultiCompUnit (and Function Units) proof
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  64   - donated
  65   - parent #195
  66
  67 ## Completed but not yet submitted:
  68
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
  70  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  71   - EUR 3000
  72   - shared with Staf 50%
  73  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
  74   - Project 2019-10-043 06dec2020 wishbone
  75   - EUR 0 (TBD)
  76
  77 ### Project 2019-10-029 14mar2020 coriolis2
  78
  79  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
  80    - (total EUR 100 shared 50% with staf)
  81    - EUR 50 lkcl
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
  83    - (total EUR 1500 shared 50% with LIP6)
  84    - EUR 750 lkcl
  85  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  86    - (total EUR 400 shared 75% with LIP6)
  87    - EUR 300 lkcl
  88
  89 ### Project 2019-02-012 06dec2020 Core
  90
  91  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
  92    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
  93  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
  94    - EUR 750 donated
  95  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
  96    - EUR 1500
  97
  98 ### Project 2019-10-043 06dec2020 wishbone
  99
 100  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 101    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 102  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 103    - EUR 200
 104  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 105    - EUR 100
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 107    - EUR 200
 108  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 109    - EUR 100
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 111    - EUR 200
 112  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 113    - EUR 450
 114  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 115    - EUR 100
 116  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 117    - EUR 200 donated
 118  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 119    - EUR 250 (share with cole)
 120
 121 ### Project 2019-10-032 06dec2020 proofs
 122
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 124    - parent #195
 125    - EUR 400 donated
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 127    - parent #195
 128    - EUR 300 donated
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 130    - EUR 400 donated
 131    - parent #195
 132  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 133    - EUR 400 donated
 134    - parent #195
 135
 136 ## Submitted for NLNet RFP
 137
 138 submitted but not confirmed paid:
 139
 140 ### Project 2019-02-012 04sep2020 Core
 141
 142  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 143    - EUR 2000 total, shared with florent.  EUR 1200
 144
 145 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 146
 147 ## Paid
 148
 149 donation from NLNet confirmed received:
 150
 151 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 152
 153  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 154     - EUR 2000, python POWER9 simulator
 155     - Shared 50% with [[mnolan]], EUR 1000
 156  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 157     - EUR 250, functions needed for simulator
 158     - Shared 20% with [[mnolan]], EUR 50
 159
 160 ### proofs 2019-10-032
 161
 162  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 163    - EUR 500 shared 20% samuel, EUR 100
 164  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 165    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 166  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 167    - EUR 400 shared 25% [[mnolan]] EUR 100
 168  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 169    - EUR 150
 170
 171 ### wishbone 2019-10-043
 172
 173  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 174    - EUR 500
 175  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 176     - EUR 300
 177  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 178     - EUR 250
 179  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 180    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 181  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 182    - EUR 300
 183  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 184    - EUR 400, 50% shared [[programmerjake]] EUR 200
 185  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 186    - EUR 750, 33% shared [[programmerjake]] EUR 250
 187  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 188    - EUR 200 50% shared, cole, EUR 100
 189  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 190    - EUR 200
 191  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 192    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 193  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 194    - EUR 150
 195  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 196    - EUR 400 shared 50% [[mnolan]] EUR 200
 197  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 198    - EUR 250 shared 40% [[mnolan]] EUR 100
 199  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 200    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 201  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 202    - EUR 300 shared 50% [[mnolan]] EUR 150
 203  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 204    - EUR 750
 205  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 206   - EUR 100
 207  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 208   - EUR 100
 209  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 210    - EUR 100
 211  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 212    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 213
 214 ### Project 2019-02-012 28-apr-2020
 215
 216  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 217    - 6600 scoreboard multi-read/write
 218    - EUR 600
 219  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 220    - Partitioned equals and greater than comparison
 221    - Shared 50% with [[mnolan]]
 222    - EUR 200 (each)
 223  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 224    - partitioned scalar/vector shift
 225    - Shared 50% with [[lkcl]]
 226    - EUR 350 (each)
 227
 228 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 229
 230  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 231     - auto-parser of POWER9
 232     - Shared 50% with [[mnolan]]
 233     - EUR 500 (each)
 234
 235 ### Project 2019-10-029 Date 14mar2020
 236
 237 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 238   - EUR 1200
 239
 240 ### Project 2019-02-012 Date 12mar2020
 241
 242 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 243 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 244 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 245 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 246
 247 ### Project 2019-02-012 Date 28jan2020
 248
 249 * admin tasks
 250 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 251