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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9
10 # Status tracking
11
12 move things along from one stage to the next
13
14 ## Currently working on
15
16 - Project Management
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
32 - EUR 150
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
34 - EUR 150
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
36 - EUR 1000
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
39 - EUR 250
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
41 - EUR 1250
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
51 - https://bugs.libre-soc.org/show_bug.cgi?id=575
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
55 - EUR
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
60 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
61 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
64 - shared with cole
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
66 - EUR 50, shared with samuel 10%
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
68
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
71 - EUR 50, shared with samuel (EUR 350)
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
77 - EUR 200
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
80 - donated
81 - parent #198
82 - EUR 200
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
84 - MultiCompUnit (and Function Units) proof
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
86 - donated
87 - parent #195
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
89
90 ## Completed but not yet submitted:
91
92 TO SORT
93
94 28feb2022
95
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
97 * EUR 1500 (shared with [[tplaten]])
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
99 * EUR 1500 (shared with [[tplaten]])
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
101 * EUR 1000 (shared with [[tplaten]])
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
103 * EUR 500 (shared with [[programmerjake]])
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
105 * EUR 400 (shared with [[programmerjake]])
106
107 before that
108
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
110 - EUR 1600
111 - EUR 800 shared with [[klehman]]
112 - EUR 800 shared with [[lkcl]]
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
114 - EUR 800
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
119 - EUR 500
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
125
126
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
128 - EUR 150
129 - donated
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
131 - EUR 200
132 - donated
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
134 - EUR 150
135 - donated
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
137 - EUR 200
138 - donated
139 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
140 - EUR 700
141 - (lip6.fr donated)
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
143 - (total EUR 400 25% donated by LIP6)
144 - EUR 100 lkcl
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
146 - EUR 900
147 - shared with [[lxo]]
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
149 - EUR 1100
150 - shared with lauri, jacob
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
152 - EUR 1250
153 - Shared 50% with Staf
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
155 - EUR 300
156 - Shared with Staf, cole
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
158 - EUR 450
159 - Shared with Staf
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
161 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
162 - Project 2019-10-043 06dec2020 wishbone
163 - EUR (TBD)
164
165 ### Project 2019-10-029 14mar2020 coriolis2
166
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
168 - (total EUR 100 shared 50% with staf)
169 - EUR 50 lkcl
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
171 - (total EUR 1500 shared 50% with LIP6)
172 - EUR 750 lkcl
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
174 - (total EUR 400 shared 75% with LIP6)
175 - EUR 300 lkcl
176
177 ### Project 2019-02-012 06dec2020 Core
178
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
180 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
181 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
182 - EUR 750 donated
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
184 - EUR 1500
185
186 ### Project 2019-10-043 06dec2020 wishbone
187
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
189 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
191 - EUR 200
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
193 - EUR 100
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
195 - EUR 200
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
197 - EUR 100
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
199 - EUR 200
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
201 - EUR 450
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
203 - EUR 100
204 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
205 - EUR 200 donated
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
207 - EUR 250 (share with cole)
208
209 ### Project 2019-10-032 06dec2020 proofs
210
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
212 - parent #195
213 - EUR 400 donated
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
215 - parent #195
216 - EUR 300 donated
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
218 - EUR 400 donated
219 - parent #195
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
221 - EUR 400 donated
222 - parent #195
223
224 ## Submitted for NLNet RFP
225
226 submitted 2021-dec-09 but not confirmed paid
227
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
229 - EUR 300
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
231 - EUR 250
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
235 - EUR 800 shared between:
236 - EUR 500 [[lkcl]]
237 - EUR 300 [[tplaten]]
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
239 - EUR 5500 shared between:
240 - EUR 3850 lkcl
241 - EUR 1650 Others
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
243 - EUR 1600
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
245 - EUR 600
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
247 - EUR 500 shared between:
248 - EUR 100 [[lkcl]]
249 - EUR 325 dmitry
250 - EUR 75 maciej
251 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
252
253
254 ### Project 2019-02-012 04sep2020 Core
255
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
257 - EUR 2000 total, shared with florent. EUR 1200
258
259 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
260
261 ## Paid
262
263 donation from NLNet confirmed received:
264
265 ### coriolis2 2021-apr-04
266
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
268 - EUR 3000
269 - shared with Staf 50%
270
271 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
272
273 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
274 - EUR 2000, python POWER9 simulator
275 - Shared 50% with [[mnolan]], EUR 1000
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
277 - EUR 250, functions needed for simulator
278 - Shared 20% with [[mnolan]], EUR 50
279
280 ### proofs 2019-10-032
281
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
283 - EUR 500 shared 20% samuel, EUR 100
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
285 - EUR 300 shared 1/6 [[mnolan]] EUR 50
286 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
287 - EUR 400 shared 25% [[mnolan]] EUR 100
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
289 - EUR 150
290
291 ### wishbone 2019-10-043
292
293 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
294 - EUR 500
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
296 - EUR 300
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
298 - EUR 250
299 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
300 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
301 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
302 - EUR 300
303 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
304 - EUR 400, 50% shared [[programmerjake]] EUR 200
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
306 - EUR 750, 33% shared [[programmerjake]] EUR 250
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
308 - EUR 200 50% shared, cole, EUR 100
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
310 - EUR 200
311 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
312 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
313 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
314 - EUR 150
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
316 - EUR 400 shared 50% [[mnolan]] EUR 200
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
318 - EUR 250 shared 40% [[mnolan]] EUR 100
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
320 - EUR 300 shared 1/3 [[mnolan]] EUR 100
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
322 - EUR 300 shared 50% [[mnolan]] EUR 150
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
324 - EUR 750
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
326 - EUR 100
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
328 - EUR 100
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
330 - EUR 100
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
332 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
333
334 ### Project 2019-02-012 28-apr-2020
335
336 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
337 - 6600 scoreboard multi-read/write
338 - EUR 600
339 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
340 - Partitioned equals and greater than comparison
341 - Shared 50% with [[mnolan]]
342 - EUR 200 (each)
343 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
344 - partitioned scalar/vector shift
345 - Shared 50% with [[lkcl]]
346 - EUR 350 (each)
347
348 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
349
350 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
351 - auto-parser of POWER9
352 - Shared 50% with [[mnolan]]
353 - EUR 500 (each)
354
355 ### Project 2019-10-029 Date 14mar2020
356
357 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
358 - EUR 1200
359
360 ### Project 2019-02-012 Date 12mar2020
361
362 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
363 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
364 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
365 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
366
367 ### Project 2019-02-012 Date 28jan2020
368
369 * admin tasks
370 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
371