1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
34 - https://bugs.libre-soc.org/show_bug.cgi?id=575
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
43 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
44 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
49 - EUR 50, shared with samuel 10%
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
54 - EUR 50, shared with samuel (EUR 350)
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
67 - MultiCompUnit (and Function Units) proof
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
73 ## Completed but not yet submitted:
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
76 - EUR 800 shared with [[klehman]]
77 - EUR 800 shared with [[lkcl]]
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
79 - EUR 500 shared between:
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
89 - EUR 800 shared between:
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
93 - EUR 5500 shared between:
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
121 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
125 - (total EUR 400 25% donated by LIP6)
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
129 - shared with [[lxo]]
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
132 - shared with lauri, jacob
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
135 - Shared 50% with Staf
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
138 - Shared with Staf, cole
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
145 - shared with Staf 50%
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
147 - Project 2019-10-043 06dec2020 wishbone
150 ### Project 2019-10-029 14mar2020 coriolis2
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
153 - (total EUR 100 shared 50% with staf)
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
156 - (total EUR 1500 shared 50% with LIP6)
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
159 - (total EUR 400 shared 75% with LIP6)
162 ### Project 2019-02-012 06dec2020 Core
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
165 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
166 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
171 ### Project 2019-10-043 06dec2020 wishbone
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
174 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
189 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
192 - EUR 250 (share with cole)
194 ### Project 2019-10-032 06dec2020 proofs
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
209 ## Submitted for NLNet RFP
211 submitted but not confirmed paid:
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
215 ### Project 2019-02-012 04sep2020 Core
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
218 - EUR 2000 total, shared with florent. EUR 1200
220 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
224 donation from NLNet confirmed received:
226 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
229 - EUR 2000, python POWER9 simulator
230 - Shared 50% with [[mnolan]], EUR 1000
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
232 - EUR 250, functions needed for simulator
233 - Shared 20% with [[mnolan]], EUR 50
235 ### proofs 2019-10-032
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
238 - EUR 500 shared 20% samuel, EUR 100
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
240 - EUR 300 shared 1/6 [[mnolan]] EUR 50
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
242 - EUR 400 shared 25% [[mnolan]] EUR 100
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
246 ### wishbone 2019-10-043
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
254 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
255 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
259 - EUR 400, 50% shared [[programmerjake]] EUR 200
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
261 - EUR 750, 33% shared [[programmerjake]] EUR 250
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
263 - EUR 200 50% shared, cole, EUR 100
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
267 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
271 - EUR 400 shared 50% [[mnolan]] EUR 200
272 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
273 - EUR 250 shared 40% [[mnolan]] EUR 100
274 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
275 - EUR 300 shared 1/3 [[mnolan]] EUR 100
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
277 - EUR 300 shared 50% [[mnolan]] EUR 150
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
280 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
286 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
287 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
289 ### Project 2019-02-012 28-apr-2020
291 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
292 - 6600 scoreboard multi-read/write
294 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
295 - Partitioned equals and greater than comparison
296 - Shared 50% with [[mnolan]]
298 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
299 - partitioned scalar/vector shift
300 - Shared 50% with [[lkcl]]
303 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
306 - auto-parser of POWER9
307 - Shared 50% with [[mnolan]]
310 ### Project 2019-10-029 Date 14mar2020
312 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
315 ### Project 2019-02-012 Date 12mar2020
317 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
318 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
319 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
320 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
322 ### Project 2019-02-012 Date 28jan2020
325 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>