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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8
9 # Status tracking
10
11 move things along from one stage to the next
12
13 ## Currently working on
14
15 - Project Management
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
20 - https://bugs.libre-soc.org/show_bug.cgi?id=575
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
24 - EUR
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
33 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
34 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
37 - shared with cole
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
39 - EUR 50, shared with samuel 10%
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
44 - EUR 50, shared with samuel (EUR 350)
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
51 - EUR 200
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
58 - donated
59 - parent #198
60 - EUR 200
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
62 - MultiCompUnit (and Function Units) proof
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
64 - donated
65 - parent #195
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
67
68 ## Completed but not yet submitted:
69
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
71 - EUR 150
72 - donated
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
74 - EUR 200
75 - donated
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
77 - EUR 150
78 - donated
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
80 - EUR 200
81 - donated
82 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
83 - EUR 700
84 - (lip6.fr donated)
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
86 - (total EUR 400 25% donated by LIP6)
87 - EUR 100 lkcl
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
89 - EUR 900
90 - shared with [[lxo]]
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
92 - EUR 1100
93 - shared with lauri, jacob
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
95 - EUR 1250
96 - Shared 50% with Staf
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
98 - EUR 300
99 - Shared with Staf, cole
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
101 - EUR 450
102 - Shared with Staf
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
105 - EUR 3000
106 - shared with Staf 50%
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
108 - Project 2019-10-043 06dec2020 wishbone
109 - EUR (TBD)
110
111 ### Project 2019-10-029 14mar2020 coriolis2
112
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
114 - (total EUR 100 shared 50% with staf)
115 - EUR 50 lkcl
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
117 - (total EUR 1500 shared 50% with LIP6)
118 - EUR 750 lkcl
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
120 - (total EUR 400 shared 75% with LIP6)
121 - EUR 300 lkcl
122
123 ### Project 2019-02-012 06dec2020 Core
124
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
126 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
127 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
128 - EUR 750 donated
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
130 - EUR 1500
131
132 ### Project 2019-10-043 06dec2020 wishbone
133
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
135 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
137 - EUR 200
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
139 - EUR 100
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
141 - EUR 200
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
143 - EUR 100
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
145 - EUR 200
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
147 - EUR 450
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
149 - EUR 100
150 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
151 - EUR 200 donated
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
153 - EUR 250 (share with cole)
154
155 ### Project 2019-10-032 06dec2020 proofs
156
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
158 - parent #195
159 - EUR 400 donated
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
161 - parent #195
162 - EUR 300 donated
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
164 - EUR 400 donated
165 - parent #195
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
167 - EUR 400 donated
168 - parent #195
169
170 ## Submitted for NLNet RFP
171
172 submitted but not confirmed paid:
173
174 ### Project 2019-02-012 04sep2020 Core
175
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
177 - EUR 2000 total, shared with florent. EUR 1200
178
179 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
180
181 ## Paid
182
183 donation from NLNet confirmed received:
184
185 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
186
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
188 - EUR 2000, python POWER9 simulator
189 - Shared 50% with [[mnolan]], EUR 1000
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
191 - EUR 250, functions needed for simulator
192 - Shared 20% with [[mnolan]], EUR 50
193
194 ### proofs 2019-10-032
195
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
197 - EUR 500 shared 20% samuel, EUR 100
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
199 - EUR 300 shared 1/6 [[mnolan]] EUR 50
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
201 - EUR 400 shared 25% [[mnolan]] EUR 100
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
203 - EUR 150
204
205 ### wishbone 2019-10-043
206
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
208 - EUR 500
209 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
210 - EUR 300
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
212 - EUR 250
213 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
214 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
216 - EUR 300
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
218 - EUR 400, 50% shared [[programmerjake]] EUR 200
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
220 - EUR 750, 33% shared [[programmerjake]] EUR 250
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
222 - EUR 200 50% shared, cole, EUR 100
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
224 - EUR 200
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
226 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
228 - EUR 150
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
230 - EUR 400 shared 50% [[mnolan]] EUR 200
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
232 - EUR 250 shared 40% [[mnolan]] EUR 100
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
234 - EUR 300 shared 1/3 [[mnolan]] EUR 100
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
236 - EUR 300 shared 50% [[mnolan]] EUR 150
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
238 - EUR 750
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
240 - EUR 100
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
242 - EUR 100
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
244 - EUR 100
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
246 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
247
248 ### Project 2019-02-012 28-apr-2020
249
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
251 - 6600 scoreboard multi-read/write
252 - EUR 600
253 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
254 - Partitioned equals and greater than comparison
255 - Shared 50% with [[mnolan]]
256 - EUR 200 (each)
257 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
258 - partitioned scalar/vector shift
259 - Shared 50% with [[lkcl]]
260 - EUR 350 (each)
261
262 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
263
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
265 - auto-parser of POWER9
266 - Shared 50% with [[mnolan]]
267 - EUR 500 (each)
268
269 ### Project 2019-10-029 Date 14mar2020
270
271 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
272 - EUR 1200
273
274 ### Project 2019-02-012 Date 12mar2020
275
276 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
277 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
278 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
279 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
280
281 ### Project 2019-02-012 Date 28jan2020
282
283 * admin tasks
284 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
285