lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
  21   - EUR 150
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
  23   - EUR 150
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
  27    - EUR 250
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
  29    - EUR 1250
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  39  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  43    - EUR
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  48  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  49  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  52    - shared with cole
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  54    - EUR 50, shared with samuel 10%
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  56
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  59    - EUR 50, shared with samuel (EUR 350)
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  65    - EUR 200
  66  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  67  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  68    - donated
  69    - parent #198
  70    - EUR 200
  71  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  72   - MultiCompUnit (and Function Units) proof
  73  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  74   - donated
  75   - parent #195
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  77
  78 ## Completed but not yet submitted:
  79
  80 TO SORT
  81
  82 28feb2022
  83
  84  - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
  85    * EUR 1500 (shared with [[tplaten]])
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
  87    * EUR 1500 (shared with [[tplaten]])
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
  89    * EUR 1000 (shared with [[tplaten]])
  90  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
  91    * EUR 500 (shared with [[programmerjake]])
  92  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  93    * EUR 400 (shared with [[programmerjake]])
  94
  95 before that
  96
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
  98    - EUR 1600
  99    - EUR 800 shared with [[klehman]]
 100    - EUR 800 shared with [[lkcl]]
 101  - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
 102    - EUR 800
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
 104  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
 107    - EUR 500
 108  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
 111  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
 112  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
 113
 114
 115  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 116    - EUR 150
 117    - donated
 118  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 119    - EUR 200
 120    - donated
 121  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 122    - EUR 150
 123    - donated
 124  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 125    - EUR 200
 126    - donated
 127  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
 128    - EUR 700
 129    - (lip6.fr donated)
 130  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 131    - (total EUR 400 25% donated by LIP6)
 132    - EUR 100 lkcl
 133  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 134    - EUR 900
 135    - shared with [[lxo]]
 136  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 137    - EUR 1100
 138    - shared with lauri, jacob
 139  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 140    - EUR 1250
 141    - Shared 50% with Staf
 142  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 143    - EUR 300
 144    - Shared with Staf, cole
 145  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 146    - EUR 450
 147    - Shared with Staf
 148  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 149  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 150    - Project 2019-10-043 06dec2020 wishbone
 151    - EUR (TBD)
 152
 153 ### Project 2019-10-029 14mar2020 coriolis2
 154
 155  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 156    - (total EUR 100 shared 50% with staf)
 157    - EUR 50 lkcl
 158  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 159    - (total EUR 1500 shared 50% with LIP6)
 160    - EUR 750 lkcl
 161  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 162    - (total EUR 400 shared 75% with LIP6)
 163    - EUR 300 lkcl
 164
 165 ### Project 2019-02-012 06dec2020 Core
 166
 167  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 168    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 169  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 170    - EUR 750 donated
 171  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 172    - EUR 1500
 173
 174 ### Project 2019-10-043 06dec2020 wishbone
 175
 176  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 177    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 178  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 179    - EUR 200
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 181    - EUR 100
 182  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 183    - EUR 200
 184  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 185    - EUR 100
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 187    - EUR 200
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 189    - EUR 450
 190  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 191    - EUR 100
 192  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 193    - EUR 200 donated
 194  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 195    - EUR 250 (share with cole)
 196
 197 ### Project 2019-10-032 06dec2020 proofs
 198
 199  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 200    - parent #195
 201    - EUR 400 donated
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 203    - parent #195
 204    - EUR 300 donated
 205  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 206    - EUR 400 donated
 207    - parent #195
 208  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 209    - EUR 400 donated
 210    - parent #195
 211
 212 ## Submitted for NLNet RFP
 213
 214 submitted 2021-dec-09 but not confirmed paid
 215
 216  - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
 217    - EUR 300
 218  - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
 219    - EUR 250
 220  - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
 221  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
 222  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
 223    - EUR 800 shared between:
 224    - EUR 500 [[lkcl]]
 225    - EUR 300 [[tplaten]]
 226  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
 227    - EUR 5500 shared between:
 228    - EUR 3850 lkcl
 229    - EUR 1650 Others
 230  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
 231    - EUR 1600
 232  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
 233    - EUR 600
 234  - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
 235    - EUR 500 shared between:
 236    - EUR 100 [[lkcl]]
 237    - EUR 325 dmitry
 238    - EUR 75 maciej
 239  - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
 240
 241
 242 ### Project 2019-02-012 04sep2020 Core
 243
 244  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 245    - EUR 2000 total, shared with florent.  EUR 1200
 246
 247 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 248
 249 ## Paid
 250
 251 donation from NLNet confirmed received:
 252
 253 ### coriolis2 2021-apr-04
 254
 255  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 256    - EUR 3000
 257    - shared with Staf 50%
 258
 259 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 260
 261  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 262     - EUR 2000, python POWER9 simulator
 263     - Shared 50% with [[mnolan]], EUR 1000
 264  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 265     - EUR 250, functions needed for simulator
 266     - Shared 20% with [[mnolan]], EUR 50
 267
 268 ### proofs 2019-10-032
 269
 270  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 271    - EUR 500 shared 20% samuel, EUR 100
 272  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 273    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 274  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 275    - EUR 400 shared 25% [[mnolan]] EUR 100
 276  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 277    - EUR 150
 278
 279 ### wishbone 2019-10-043
 280
 281  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 282    - EUR 500
 283  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 284     - EUR 300
 285  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 286     - EUR 250
 287  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 288    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 289  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 290    - EUR 300
 291  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 292    - EUR 400, 50% shared [[programmerjake]] EUR 200
 293  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 294    - EUR 750, 33% shared [[programmerjake]] EUR 250
 295  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 296    - EUR 200 50% shared, cole, EUR 100
 297  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 298    - EUR 200
 299  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 300    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 301  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 302    - EUR 150
 303  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 304    - EUR 400 shared 50% [[mnolan]] EUR 200
 305  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 306    - EUR 250 shared 40% [[mnolan]] EUR 100
 307  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 308    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 309  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 310    - EUR 300 shared 50% [[mnolan]] EUR 150
 311  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 312    - EUR 750
 313  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 314   - EUR 100
 315  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 316   - EUR 100
 317  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 318    - EUR 100
 319  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 320    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 321
 322 ### Project 2019-02-012 28-apr-2020
 323
 324  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 325    - 6600 scoreboard multi-read/write
 326    - EUR 600
 327  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 328    - Partitioned equals and greater than comparison
 329    - Shared 50% with [[mnolan]]
 330    - EUR 200 (each)
 331  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 332    - partitioned scalar/vector shift
 333    - Shared 50% with [[lkcl]]
 334    - EUR 350 (each)
 335
 336 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 337
 338  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 339     - auto-parser of POWER9
 340     - Shared 50% with [[mnolan]]
 341     - EUR 500 (each)
 342
 343 ### Project 2019-10-029 Date 14mar2020
 344
 345 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 346   - EUR 1200
 347
 348 ### Project 2019-02-012 Date 12mar2020
 349
 350 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 351 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 352 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 353 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 354
 355 ### Project 2019-02-012 Date 28jan2020
 356
 357 * admin tasks
 358 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 359