lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  26  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  30    - EUR
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  38  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  39  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  42    - shared with cole
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  44    - EUR 50, shared with samuel 10%
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  49    - EUR 50, shared with samuel (EUR 350)
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  56    - EUR 200
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  59    - donated
  60    - parent #198
  61    - EUR 200
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  63   - MultiCompUnit (and Function Units) proof
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  65   - donated
  66   - parent #195
  67  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  68
  69 ## Completed but not yet submitted:
  70  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
  71  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
  72    - EUR 1600
  73  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  74  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  75  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  77  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  78
  79
  80  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
  81    - EUR 150
  82    - donated
  83  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
  84    - EUR 200
  85    - donated
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
  87    - EUR 150
  88    - donated
  89  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
  90    - EUR 200
  91    - donated
  92  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
  93    - EUR 700
  94    - (lip6.fr donated)
  95  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  96    - (total EUR 400 25% donated by LIP6)
  97    - EUR 100 lkcl
  98  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  99    - EUR 900
 100    - shared with [[lxo]]
 101  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 102    - EUR 1100
 103    - shared with lauri, jacob
 104  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 105    - EUR 1250
 106    - Shared 50% with Staf
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 108    - EUR 300
 109    - Shared with Staf, cole
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 111    - EUR 450
 112    - Shared with Staf
 113  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 114  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 115    - EUR 3000
 116    - shared with Staf 50%
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 118    - Project 2019-10-043 06dec2020 wishbone
 119    - EUR (TBD)
 120
 121 ### Project 2019-10-029 14mar2020 coriolis2
 122
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 124    - (total EUR 100 shared 50% with staf)
 125    - EUR 50 lkcl
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 127    - (total EUR 1500 shared 50% with LIP6)
 128    - EUR 750 lkcl
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 130    - (total EUR 400 shared 75% with LIP6)
 131    - EUR 300 lkcl
 132
 133 ### Project 2019-02-012 06dec2020 Core
 134
 135  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 136    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 137  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 138    - EUR 750 donated
 139  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 140    - EUR 1500
 141
 142 ### Project 2019-10-043 06dec2020 wishbone
 143
 144  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 145    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 146  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 147    - EUR 200
 148  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 149    - EUR 100
 150  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 151    - EUR 200
 152  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 153    - EUR 100
 154  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 155    - EUR 200
 156  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 157    - EUR 450
 158  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 159    - EUR 100
 160  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 161    - EUR 200 donated
 162  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 163    - EUR 250 (share with cole)
 164
 165 ### Project 2019-10-032 06dec2020 proofs
 166
 167  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 168    - parent #195
 169    - EUR 400 donated
 170  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 171    - parent #195
 172    - EUR 300 donated
 173  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 174    - EUR 400 donated
 175    - parent #195
 176  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 177    - EUR 400 donated
 178    - parent #195
 179
 180 ## Submitted for NLNet RFP
 181
 182 submitted but not confirmed paid:
 183
 184 ### Project 2019-02-012 04sep2020 Core
 185
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 187    - EUR 2000 total, shared with florent.  EUR 1200
 188
 189 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 190
 191 ## Paid
 192
 193 donation from NLNet confirmed received:
 194
 195 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 196
 197  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 198     - EUR 2000, python POWER9 simulator
 199     - Shared 50% with [[mnolan]], EUR 1000
 200  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 201     - EUR 250, functions needed for simulator
 202     - Shared 20% with [[mnolan]], EUR 50
 203
 204 ### proofs 2019-10-032
 205
 206  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 207    - EUR 500 shared 20% samuel, EUR 100
 208  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 209    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 210  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 211    - EUR 400 shared 25% [[mnolan]] EUR 100
 212  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 213    - EUR 150
 214
 215 ### wishbone 2019-10-043
 216
 217  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 218    - EUR 500
 219  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 220     - EUR 300
 221  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 222     - EUR 250
 223  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 224    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 225  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 226    - EUR 300
 227  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 228    - EUR 400, 50% shared [[programmerjake]] EUR 200
 229  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 230    - EUR 750, 33% shared [[programmerjake]] EUR 250
 231  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 232    - EUR 200 50% shared, cole, EUR 100
 233  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 234    - EUR 200
 235  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 236    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 237  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 238    - EUR 150
 239  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 240    - EUR 400 shared 50% [[mnolan]] EUR 200
 241  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 242    - EUR 250 shared 40% [[mnolan]] EUR 100
 243  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 244    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 245  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 246    - EUR 300 shared 50% [[mnolan]] EUR 150
 247  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 248    - EUR 750
 249  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 250   - EUR 100
 251  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 252   - EUR 100
 253  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 254    - EUR 100
 255  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 256    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 257
 258 ### Project 2019-02-012 28-apr-2020
 259
 260  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 261    - 6600 scoreboard multi-read/write
 262    - EUR 600
 263  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 264    - Partitioned equals and greater than comparison
 265    - Shared 50% with [[mnolan]]
 266    - EUR 200 (each)
 267  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 268    - partitioned scalar/vector shift
 269    - Shared 50% with [[lkcl]]
 270    - EUR 350 (each)
 271
 272 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 273
 274  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 275     - auto-parser of POWER9
 276     - Shared 50% with [[mnolan]]
 277     - EUR 500 (each)
 278
 279 ### Project 2019-10-029 Date 14mar2020
 280
 281 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 282   - EUR 1200
 283
 284 ### Project 2019-02-012 Date 12mar2020
 285
 286 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 287 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 288 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 289 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 290
 291 ### Project 2019-02-012 Date 28jan2020
 292
 293 * admin tasks
 294 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 295