lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  26  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  30    - EUR
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  39  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  40  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  43    - shared with cole
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  45    - EUR 50, shared with samuel 10%
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  50    - EUR 50, shared with samuel (EUR 350)
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  57    - EUR 200
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  64    - donated
  65    - parent #198
  66    - EUR 200
  67  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  68   - MultiCompUnit (and Function Units) proof
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  70   - donated
  71   - parent #195
  72  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  73
  74 ## Completed but not yet submitted:
  75
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
  77    - EUR 150
  78    - donated
  79  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
  80    - EUR 200
  81    - donated
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
  83    - EUR 150
  84    - donated
  85  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
  86    - EUR 200
  87    - donated
  88  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
  89    - EUR 700
  90    - (lip6.fr donated)
  91  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  92    - (total EUR 400 25% donated by LIP6)
  93    - EUR 100 lkcl
  94  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  95    - EUR 900
  96    - shared with [[lxo]]
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
  98    - EUR 1100
  99    - shared with lauri, jacob
 100  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 101    - EUR 1250
 102    - Shared 50% with Staf
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 104    - EUR 300
 105    - Shared with Staf, cole
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 107    - EUR 450
 108    - Shared with Staf
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 111    - EUR 3000
 112    - shared with Staf 50%
 113  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 114    - Project 2019-10-043 06dec2020 wishbone
 115    - EUR (TBD)
 116
 117 ### Project 2019-10-029 14mar2020 coriolis2
 118
 119  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 120    - (total EUR 100 shared 50% with staf)
 121    - EUR 50 lkcl
 122  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 123    - (total EUR 1500 shared 50% with LIP6)
 124    - EUR 750 lkcl
 125  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 126    - (total EUR 400 shared 75% with LIP6)
 127    - EUR 300 lkcl
 128
 129 ### Project 2019-02-012 06dec2020 Core
 130
 131  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 132    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 133  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 134    - EUR 750 donated
 135  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 136    - EUR 1500
 137
 138 ### Project 2019-10-043 06dec2020 wishbone
 139
 140  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 141    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 142  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 143    - EUR 200
 144  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 145    - EUR 100
 146  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 147    - EUR 200
 148  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 149    - EUR 100
 150  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 151    - EUR 200
 152  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 153    - EUR 450
 154  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 155    - EUR 100
 156  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 157    - EUR 200 donated
 158  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 159    - EUR 250 (share with cole)
 160
 161 ### Project 2019-10-032 06dec2020 proofs
 162
 163  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 164    - parent #195
 165    - EUR 400 donated
 166  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 167    - parent #195
 168    - EUR 300 donated
 169  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 170    - EUR 400 donated
 171    - parent #195
 172  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 173    - EUR 400 donated
 174    - parent #195
 175
 176 ## Submitted for NLNet RFP
 177
 178 submitted but not confirmed paid:
 179
 180 ### Project 2019-02-012 04sep2020 Core
 181
 182  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 183    - EUR 2000 total, shared with florent.  EUR 1200
 184
 185 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 186
 187 ## Paid
 188
 189 donation from NLNet confirmed received:
 190
 191 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 192
 193  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 194     - EUR 2000, python POWER9 simulator
 195     - Shared 50% with [[mnolan]], EUR 1000
 196  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 197     - EUR 250, functions needed for simulator
 198     - Shared 20% with [[mnolan]], EUR 50
 199
 200 ### proofs 2019-10-032
 201
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 203    - EUR 500 shared 20% samuel, EUR 100
 204  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 205    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 206  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 207    - EUR 400 shared 25% [[mnolan]] EUR 100
 208  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 209    - EUR 150
 210
 211 ### wishbone 2019-10-043
 212
 213  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 214    - EUR 500
 215  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 216     - EUR 300
 217  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 218     - EUR 250
 219  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 220    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 221  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 222    - EUR 300
 223  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 224    - EUR 400, 50% shared [[programmerjake]] EUR 200
 225  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 226    - EUR 750, 33% shared [[programmerjake]] EUR 250
 227  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 228    - EUR 200 50% shared, cole, EUR 100
 229  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 230    - EUR 200
 231  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 232    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 233  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 234    - EUR 150
 235  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 236    - EUR 400 shared 50% [[mnolan]] EUR 200
 237  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 238    - EUR 250 shared 40% [[mnolan]] EUR 100
 239  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 240    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 241  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 242    - EUR 300 shared 50% [[mnolan]] EUR 150
 243  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 244    - EUR 750
 245  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 246   - EUR 100
 247  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 248   - EUR 100
 249  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 250    - EUR 100
 251  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 252    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 253
 254 ### Project 2019-02-012 28-apr-2020
 255
 256  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 257    - 6600 scoreboard multi-read/write
 258    - EUR 600
 259  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 260    - Partitioned equals and greater than comparison
 261    - Shared 50% with [[mnolan]]
 262    - EUR 200 (each)
 263  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 264    - partitioned scalar/vector shift
 265    - Shared 50% with [[lkcl]]
 266    - EUR 350 (each)
 267
 268 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 269
 270  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 271     - auto-parser of POWER9
 272     - Shared 50% with [[mnolan]]
 273     - EUR 500 (each)
 274
 275 ### Project 2019-10-029 Date 14mar2020
 276
 277 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 278   - EUR 1200
 279
 280 ### Project 2019-02-012 Date 12mar2020
 281
 282 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 283 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 284 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 285 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 286
 287 ### Project 2019-02-012 Date 28jan2020
 288
 289 * admin tasks
 290 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 291