1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
25 - https://bugs.libre-soc.org/show_bug.cgi?id=575
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
37 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
38 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
43 - EUR 50, shared with samuel 10%
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
48 - EUR 50, shared with samuel (EUR 350)
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
62 - MultiCompUnit (and Function Units) proof
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
68 ## Completed but not yet submitted:
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
90 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
94 - (total EUR 400 25% donated by LIP6)
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
101 - shared with lauri, jacob
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
104 - Shared 50% with Staf
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
107 - Shared with Staf, cole
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
114 - shared with Staf 50%
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
116 - Project 2019-10-043 06dec2020 wishbone
119 ### Project 2019-10-029 14mar2020 coriolis2
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
122 - (total EUR 100 shared 50% with staf)
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
125 - (total EUR 1500 shared 50% with LIP6)
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
128 - (total EUR 400 shared 75% with LIP6)
131 ### Project 2019-02-012 06dec2020 Core
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
134 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
135 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
140 ### Project 2019-10-043 06dec2020 wishbone
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
143 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
158 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
161 - EUR 250 (share with cole)
163 ### Project 2019-10-032 06dec2020 proofs
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
178 ## Submitted for NLNet RFP
180 submitted but not confirmed paid:
182 ### Project 2019-02-012 04sep2020 Core
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
185 - EUR 2000 total, shared with florent. EUR 1200
187 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
191 donation from NLNet confirmed received:
193 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
196 - EUR 2000, python POWER9 simulator
197 - Shared 50% with [[mnolan]], EUR 1000
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
199 - EUR 250, functions needed for simulator
200 - Shared 20% with [[mnolan]], EUR 50
202 ### proofs 2019-10-032
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
205 - EUR 500 shared 20% samuel, EUR 100
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
207 - EUR 300 shared 1/6 [[mnolan]] EUR 50
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
209 - EUR 400 shared 25% [[mnolan]] EUR 100
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
213 ### wishbone 2019-10-043
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
221 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
222 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
226 - EUR 400, 50% shared [[programmerjake]] EUR 200
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
228 - EUR 750, 33% shared [[programmerjake]] EUR 250
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
230 - EUR 200 50% shared, cole, EUR 100
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
234 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
238 - EUR 400 shared 50% [[mnolan]] EUR 200
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
240 - EUR 250 shared 40% [[mnolan]] EUR 100
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
242 - EUR 300 shared 1/3 [[mnolan]] EUR 100
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
244 - EUR 300 shared 50% [[mnolan]] EUR 150
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
247 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
249 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
251 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
254 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
256 ### Project 2019-02-012 28-apr-2020
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
259 - 6600 scoreboard multi-read/write
261 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
262 - Partitioned equals and greater than comparison
263 - Shared 50% with [[mnolan]]
265 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
266 - partitioned scalar/vector shift
267 - Shared 50% with [[lkcl]]
270 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
272 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
273 - auto-parser of POWER9
274 - Shared 50% with [[mnolan]]
277 ### Project 2019-10-029 Date 14mar2020
279 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
282 ### Project 2019-02-012 Date 12mar2020
284 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
285 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
286 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
287 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
289 ### Project 2019-02-012 Date 28jan2020
292 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>