lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7
   8 # Status tracking
   9
  10 move things along from one stage to the next
  11
  12 ## Currently working on
  13
  14  - Project Management
  15  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  16  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  17  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documrntation
  21    - EUR
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  23    - EUR
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  33  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  34  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  37    - shared with cole
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  39    - EUR 50, shared with samuel 10%
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  44    - EUR 50, shared with samuel (EUR 350)
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  51    - EUR 200
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  58    - donated
  59    - parent #198
  60    - EUR 200
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  62   - MultiCompUnit (and Function Units) proof
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  64   - donated
  65   - parent #195
  66
  67 ## Completed but not yet submitted:
  68
  69 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
  70    - EUR 1250
  71    - Shared 50% with Staf
  72  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
  73  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  74    - EUR 3000
  75    - shared with Staf 50%
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
  77    - Project 2019-10-043 06dec2020 wishbone
  78    - EUR (TBD)
  79
  80 ### Project 2019-10-029 14mar2020 coriolis2
  81
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
  83    - (total EUR 100 shared 50% with staf)
  84    - EUR 50 lkcl
  85  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
  86    - (total EUR 1500 shared 50% with LIP6)
  87    - EUR 750 lkcl
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  89    - (total EUR 400 shared 75% with LIP6)
  90    - EUR 300 lkcl
  91
  92 ### Project 2019-02-012 06dec2020 Core
  93
  94  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
  95    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
  96  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
  97    - EUR 750 donated
  98  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
  99    - EUR 1500
 100
 101 ### Project 2019-10-043 06dec2020 wishbone
 102
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 104    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 106    - EUR 200
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 108    - EUR 100
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 110    - EUR 200
 111  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 112    - EUR 100
 113  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 114    - EUR 200
 115  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 116    - EUR 450
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 118    - EUR 100
 119  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 120    - EUR 200 donated
 121  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 122    - EUR 250 (share with cole)
 123
 124 ### Project 2019-10-032 06dec2020 proofs
 125
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 127    - parent #195
 128    - EUR 400 donated
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 130    - parent #195
 131    - EUR 300 donated
 132  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 133    - EUR 400 donated
 134    - parent #195
 135  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 136    - EUR 400 donated
 137    - parent #195
 138
 139 ## Submitted for NLNet RFP
 140
 141 submitted but not confirmed paid:
 142
 143 ### Project 2019-02-012 04sep2020 Core
 144
 145  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 146    - EUR 2000 total, shared with florent.  EUR 1200
 147
 148 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 149
 150 ## Paid
 151
 152 donation from NLNet confirmed received:
 153
 154 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 155
 156  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 157     - EUR 2000, python POWER9 simulator
 158     - Shared 50% with [[mnolan]], EUR 1000
 159  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 160     - EUR 250, functions needed for simulator
 161     - Shared 20% with [[mnolan]], EUR 50
 162
 163 ### proofs 2019-10-032
 164
 165  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 166    - EUR 500 shared 20% samuel, EUR 100
 167  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 168    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 169  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 170    - EUR 400 shared 25% [[mnolan]] EUR 100
 171  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 172    - EUR 150
 173
 174 ### wishbone 2019-10-043
 175
 176  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 177    - EUR 500
 178  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 179     - EUR 300
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 181     - EUR 250
 182  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 183    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 184  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 185    - EUR 300
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 187    - EUR 400, 50% shared [[programmerjake]] EUR 200
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 189    - EUR 750, 33% shared [[programmerjake]] EUR 250
 190  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 191    - EUR 200 50% shared, cole, EUR 100
 192  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 193    - EUR 200
 194  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 195    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 196  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 197    - EUR 150
 198  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 199    - EUR 400 shared 50% [[mnolan]] EUR 200
 200  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 201    - EUR 250 shared 40% [[mnolan]] EUR 100
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 203    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 204  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 205    - EUR 300 shared 50% [[mnolan]] EUR 150
 206  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 207    - EUR 750
 208  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 209   - EUR 100
 210  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 211   - EUR 100
 212  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 213    - EUR 100
 214  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 215    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 216
 217 ### Project 2019-02-012 28-apr-2020
 218
 219  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 220    - 6600 scoreboard multi-read/write
 221    - EUR 600
 222  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 223    - Partitioned equals and greater than comparison
 224    - Shared 50% with [[mnolan]]
 225    - EUR 200 (each)
 226  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 227    - partitioned scalar/vector shift
 228    - Shared 50% with [[lkcl]]
 229    - EUR 350 (each)
 230
 231 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 232
 233  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 234     - auto-parser of POWER9
 235     - Shared 50% with [[mnolan]]
 236     - EUR 500 (each)
 237
 238 ### Project 2019-10-029 Date 14mar2020
 239
 240 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 241   - EUR 1200
 242
 243 ### Project 2019-02-012 Date 12mar2020
 244
 245 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 246 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 247 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 248 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 249
 250 ### Project 2019-02-012 Date 28jan2020
 251
 252 * admin tasks
 253 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 254