lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
  20    - EUR 250
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
  22    - EUR 1250
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  32  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  36    - EUR
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  41  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  42  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  45    - shared with cole
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  47    - EUR 50, shared with samuel 10%
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  52    - EUR 50, shared with samuel (EUR 350)
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  58    - EUR 200
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  61    - donated
  62    - parent #198
  63    - EUR 200
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  65   - MultiCompUnit (and Function Units) proof
  66  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  67   - donated
  68   - parent #195
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  70
  71 ## Completed but not yet submitted:
  72
  73 TO SORT
  74
  75 28feb2022
  76
  77  - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
  78  - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
  79  - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
  80  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
  81
  82 before that
  83
  84  - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
  85    - EUR 1600
  86    - EUR 800 shared with [[klehman]]
  87    - EUR 800 shared with [[lkcl]]
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
  89    - EUR 800
  90  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  91  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
  92  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
  93  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
  94    - EUR 500
  95  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  96  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  98  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  99  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
 100
 101
 102  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 103    - EUR 150
 104    - donated
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 106    - EUR 200
 107    - donated
 108  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 109    - EUR 150
 110    - donated
 111  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 112    - EUR 200
 113    - donated
 114  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
 115    - EUR 700
 116    - (lip6.fr donated)
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 118    - (total EUR 400 25% donated by LIP6)
 119    - EUR 100 lkcl
 120  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 121    - EUR 900
 122    - shared with [[lxo]]
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 124    - EUR 1100
 125    - shared with lauri, jacob
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 127    - EUR 1250
 128    - Shared 50% with Staf
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 130    - EUR 300
 131    - Shared with Staf, cole
 132  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 133    - EUR 450
 134    - Shared with Staf
 135  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 136  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 137    - Project 2019-10-043 06dec2020 wishbone
 138    - EUR (TBD)
 139
 140 ### Project 2019-10-029 14mar2020 coriolis2
 141
 142  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 143    - (total EUR 100 shared 50% with staf)
 144    - EUR 50 lkcl
 145  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 146    - (total EUR 1500 shared 50% with LIP6)
 147    - EUR 750 lkcl
 148  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 149    - (total EUR 400 shared 75% with LIP6)
 150    - EUR 300 lkcl
 151
 152 ### Project 2019-02-012 06dec2020 Core
 153
 154  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 155    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 156  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 157    - EUR 750 donated
 158  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 159    - EUR 1500
 160
 161 ### Project 2019-10-043 06dec2020 wishbone
 162
 163  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 164    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 165  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 166    - EUR 200
 167  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 168    - EUR 100
 169  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 170    - EUR 200
 171  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 172    - EUR 100
 173  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 174    - EUR 200
 175  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 176    - EUR 450
 177  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 178    - EUR 100
 179  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 180    - EUR 200 donated
 181  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 182    - EUR 250 (share with cole)
 183
 184 ### Project 2019-10-032 06dec2020 proofs
 185
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 187    - parent #195
 188    - EUR 400 donated
 189  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 190    - parent #195
 191    - EUR 300 donated
 192  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 193    - EUR 400 donated
 194    - parent #195
 195  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 196    - EUR 400 donated
 197    - parent #195
 198
 199 ## Submitted for NLNet RFP
 200
 201 submitted 2021-dec-09 but not confirmed paid
 202
 203  - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
 204    - EUR 300
 205  - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
 206    - EUR 250
 207  - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
 208  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
 209  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
 210    - EUR 800 shared between:
 211    - EUR 500 [[lkcl]]
 212    - EUR 300 [[tplaten]]
 213  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
 214    - EUR 5500 shared between:
 215    - EUR 3850 lkcl
 216    - EUR 1650 Others
 217  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
 218    - EUR 1600
 219  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
 220    - EUR 600
 221  - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
 222    - EUR 500 shared between:
 223    - EUR 100 [[lkcl]]
 224    - EUR 325 dmitry
 225    - EUR 75 maciej
 226  - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
 227
 228
 229 ### Project 2019-02-012 04sep2020 Core
 230
 231  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 232    - EUR 2000 total, shared with florent.  EUR 1200
 233
 234 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 235
 236 ## Paid
 237
 238 donation from NLNet confirmed received:
 239
 240 ### coriolis2 2021-apr-04
 241
 242  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 243    - EUR 3000
 244    - shared with Staf 50%
 245
 246 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 247
 248  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 249     - EUR 2000, python POWER9 simulator
 250     - Shared 50% with [[mnolan]], EUR 1000
 251  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 252     - EUR 250, functions needed for simulator
 253     - Shared 20% with [[mnolan]], EUR 50
 254
 255 ### proofs 2019-10-032
 256
 257  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 258    - EUR 500 shared 20% samuel, EUR 100
 259  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 260    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 261  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 262    - EUR 400 shared 25% [[mnolan]] EUR 100
 263  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 264    - EUR 150
 265
 266 ### wishbone 2019-10-043
 267
 268  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 269    - EUR 500
 270  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 271     - EUR 300
 272  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 273     - EUR 250
 274  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 275    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 276  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 277    - EUR 300
 278  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 279    - EUR 400, 50% shared [[programmerjake]] EUR 200
 280  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 281    - EUR 750, 33% shared [[programmerjake]] EUR 250
 282  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 283    - EUR 200 50% shared, cole, EUR 100
 284  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 285    - EUR 200
 286  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 287    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 288  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 289    - EUR 150
 290  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 291    - EUR 400 shared 50% [[mnolan]] EUR 200
 292  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 293    - EUR 250 shared 40% [[mnolan]] EUR 100
 294  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 295    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 296  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 297    - EUR 300 shared 50% [[mnolan]] EUR 150
 298  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 299    - EUR 750
 300  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 301   - EUR 100
 302  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 303   - EUR 100
 304  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 305    - EUR 100
 306  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 307    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 308
 309 ### Project 2019-02-012 28-apr-2020
 310
 311  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 312    - 6600 scoreboard multi-read/write
 313    - EUR 600
 314  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 315    - Partitioned equals and greater than comparison
 316    - Shared 50% with [[mnolan]]
 317    - EUR 200 (each)
 318  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 319    - partitioned scalar/vector shift
 320    - Shared 50% with [[lkcl]]
 321    - EUR 350 (each)
 322
 323 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 324
 325  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 326     - auto-parser of POWER9
 327     - Shared 50% with [[mnolan]]
 328     - EUR 500 (each)
 329
 330 ### Project 2019-10-029 Date 14mar2020
 331
 332 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 333   - EUR 1200
 334
 335 ### Project 2019-02-012 Date 12mar2020
 336
 337 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 338 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 339 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 340 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 341
 342 ### Project 2019-02-012 Date 28jan2020
 343
 344 * admin tasks
 345 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 346