lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7
   8 # Status tracking
   9
  10 move things along from one stage to the next
  11
  12 ## Currently working on
  13
  14  - Project Management
  15  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  16  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  17  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  21    - EUR
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  30  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  31  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  34    - shared with cole
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  36    - EUR 50, shared with samuel 10%
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  41    - EUR 50, shared with samuel (EUR 350)
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  48    - EUR 200
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  55    - donated
  56    - parent #198
  57    - EUR 200
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  59   - MultiCompUnit (and Function Units) proof
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  61   - donated
  62   - parent #195
  63
  64 ## Completed but not yet submitted:
  65
  66  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  67    - (total EUR 400 25% donated by LIP6)
  68    - EUR 100 lkcl
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  70    - EUR 900
  71    - shared with [[lxo]]
  72  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
  73    - EUR 1100
  74    - shared with lauri, jacob
  75  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
  76    - EUR 1250
  77    - Shared 50% with Staf
  78  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
  79    - EUR 300
  80    - Shared with Staf, cole
  81  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
  82    - EUR 450
  83    - Shared with Staf
  84  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
  85  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  86    - EUR 3000
  87    - shared with Staf 50%
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
  89    - Project 2019-10-043 06dec2020 wishbone
  90    - EUR (TBD)
  91
  92 ### Project 2019-10-029 14mar2020 coriolis2
  93
  94  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
  95    - (total EUR 100 shared 50% with staf)
  96    - EUR 50 lkcl
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
  98    - (total EUR 1500 shared 50% with LIP6)
  99    - EUR 750 lkcl
 100  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 101    - (total EUR 400 shared 75% with LIP6)
 102    - EUR 300 lkcl
 103
 104 ### Project 2019-02-012 06dec2020 Core
 105
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 107    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 108  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 109    - EUR 750 donated
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 111    - EUR 1500
 112
 113 ### Project 2019-10-043 06dec2020 wishbone
 114
 115  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 116    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 118    - EUR 200
 119  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 120    - EUR 100
 121  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 122    - EUR 200
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 124    - EUR 100
 125  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 126    - EUR 200
 127  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 128    - EUR 450
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 130    - EUR 100
 131  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 132    - EUR 200 donated
 133  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 134    - EUR 250 (share with cole)
 135
 136 ### Project 2019-10-032 06dec2020 proofs
 137
 138  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 139    - parent #195
 140    - EUR 400 donated
 141  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 142    - parent #195
 143    - EUR 300 donated
 144  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 145    - EUR 400 donated
 146    - parent #195
 147  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 148    - EUR 400 donated
 149    - parent #195
 150
 151 ## Submitted for NLNet RFP
 152
 153 submitted but not confirmed paid:
 154
 155 ### Project 2019-02-012 04sep2020 Core
 156
 157  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 158    - EUR 2000 total, shared with florent.  EUR 1200
 159
 160 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 161
 162 ## Paid
 163
 164 donation from NLNet confirmed received:
 165
 166 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 167
 168  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 169     - EUR 2000, python POWER9 simulator
 170     - Shared 50% with [[mnolan]], EUR 1000
 171  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 172     - EUR 250, functions needed for simulator
 173     - Shared 20% with [[mnolan]], EUR 50
 174
 175 ### proofs 2019-10-032
 176
 177  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 178    - EUR 500 shared 20% samuel, EUR 100
 179  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 180    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 181  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 182    - EUR 400 shared 25% [[mnolan]] EUR 100
 183  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 184    - EUR 150
 185
 186 ### wishbone 2019-10-043
 187
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 189    - EUR 500
 190  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 191     - EUR 300
 192  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 193     - EUR 250
 194  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 195    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 196  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 197    - EUR 300
 198  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 199    - EUR 400, 50% shared [[programmerjake]] EUR 200
 200  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 201    - EUR 750, 33% shared [[programmerjake]] EUR 250
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 203    - EUR 200 50% shared, cole, EUR 100
 204  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 205    - EUR 200
 206  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 207    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 208  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 209    - EUR 150
 210  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 211    - EUR 400 shared 50% [[mnolan]] EUR 200
 212  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 213    - EUR 250 shared 40% [[mnolan]] EUR 100
 214  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 215    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 216  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 217    - EUR 300 shared 50% [[mnolan]] EUR 150
 218  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 219    - EUR 750
 220  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 221   - EUR 100
 222  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 223   - EUR 100
 224  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 225    - EUR 100
 226  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 227    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 228
 229 ### Project 2019-02-012 28-apr-2020
 230
 231  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 232    - 6600 scoreboard multi-read/write
 233    - EUR 600
 234  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 235    - Partitioned equals and greater than comparison
 236    - Shared 50% with [[mnolan]]
 237    - EUR 200 (each)
 238  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 239    - partitioned scalar/vector shift
 240    - Shared 50% with [[lkcl]]
 241    - EUR 350 (each)
 242
 243 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 244
 245  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 246     - auto-parser of POWER9
 247     - Shared 50% with [[mnolan]]
 248     - EUR 500 (each)
 249
 250 ### Project 2019-10-029 Date 14mar2020
 251
 252 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 253   - EUR 1200
 254
 255 ### Project 2019-02-012 Date 12mar2020
 256
 257 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 258 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 259 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 260 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 261
 262 ### Project 2019-02-012 Date 28jan2020
 263
 264 * admin tasks
 265 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 266