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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9
10 # Status tracking
11
12 move things along from one stage to the next
13
14 ## Currently working on
15
16 - Project Management
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
25 - EUR 150
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
27 - EUR 150
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
29 - EUR 1000
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
32 - EUR 250
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
34 - EUR 1250
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
44 - https://bugs.libre-soc.org/show_bug.cgi?id=575
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
48 - EUR
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
53 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
54 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
57 - shared with cole
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
59 - EUR 50, shared with samuel 10%
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
61
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
64 - EUR 50, shared with samuel (EUR 350)
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
70 - EUR 200
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
73 - donated
74 - parent #198
75 - EUR 200
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
77 - MultiCompUnit (and Function Units) proof
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
79 - donated
80 - parent #195
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
82
83 ## Completed but not yet submitted:
84
85 TO SORT
86
87 28feb2022
88
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
90 * EUR 1500 (shared with [[tplaten]])
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
92 * EUR 1500 (shared with [[tplaten]])
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
94 * EUR 1000 (shared with [[tplaten]])
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
96 * EUR 500 (shared with [[programmerjake]])
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
98 * EUR 400 (shared with [[programmerjake]])
99
100 before that
101
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
103 - EUR 1600
104 - EUR 800 shared with [[klehman]]
105 - EUR 800 shared with [[lkcl]]
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
107 - EUR 800
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
112 - EUR 500
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
118
119
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
121 - EUR 150
122 - donated
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
124 - EUR 200
125 - donated
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
127 - EUR 150
128 - donated
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
130 - EUR 200
131 - donated
132 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
133 - EUR 700
134 - (lip6.fr donated)
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
136 - (total EUR 400 25% donated by LIP6)
137 - EUR 100 lkcl
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
139 - EUR 900
140 - shared with [[lxo]]
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
142 - EUR 1100
143 - shared with lauri, jacob
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
145 - EUR 1250
146 - Shared 50% with Staf
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
148 - EUR 300
149 - Shared with Staf, cole
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
151 - EUR 450
152 - Shared with Staf
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
155 - Project 2019-10-043 06dec2020 wishbone
156 - EUR (TBD)
157
158 ### Project 2019-10-029 14mar2020 coriolis2
159
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
161 - (total EUR 100 shared 50% with staf)
162 - EUR 50 lkcl
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
164 - (total EUR 1500 shared 50% with LIP6)
165 - EUR 750 lkcl
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
167 - (total EUR 400 shared 75% with LIP6)
168 - EUR 300 lkcl
169
170 ### Project 2019-02-012 06dec2020 Core
171
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
173 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
174 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
175 - EUR 750 donated
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
177 - EUR 1500
178
179 ### Project 2019-10-043 06dec2020 wishbone
180
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
182 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
184 - EUR 200
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
186 - EUR 100
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
188 - EUR 200
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
190 - EUR 100
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
192 - EUR 200
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
194 - EUR 450
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
196 - EUR 100
197 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
198 - EUR 200 donated
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
200 - EUR 250 (share with cole)
201
202 ### Project 2019-10-032 06dec2020 proofs
203
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
205 - parent #195
206 - EUR 400 donated
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
208 - parent #195
209 - EUR 300 donated
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
211 - EUR 400 donated
212 - parent #195
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
214 - EUR 400 donated
215 - parent #195
216
217 ## Submitted for NLNet RFP
218
219 submitted 2021-dec-09 but not confirmed paid
220
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
222 - EUR 300
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
224 - EUR 250
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
228 - EUR 800 shared between:
229 - EUR 500 [[lkcl]]
230 - EUR 300 [[tplaten]]
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
232 - EUR 5500 shared between:
233 - EUR 3850 lkcl
234 - EUR 1650 Others
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
236 - EUR 1600
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
238 - EUR 600
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
240 - EUR 500 shared between:
241 - EUR 100 [[lkcl]]
242 - EUR 325 dmitry
243 - EUR 75 maciej
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
245
246
247 ### Project 2019-02-012 04sep2020 Core
248
249 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
250 - EUR 2000 total, shared with florent. EUR 1200
251
252 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
253
254 ## Paid
255
256 donation from NLNet confirmed received:
257
258 ### coriolis2 2021-apr-04
259
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
261 - EUR 3000
262 - shared with Staf 50%
263
264 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
265
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
267 - EUR 2000, python POWER9 simulator
268 - Shared 50% with [[mnolan]], EUR 1000
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
270 - EUR 250, functions needed for simulator
271 - Shared 20% with [[mnolan]], EUR 50
272
273 ### proofs 2019-10-032
274
275 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
276 - EUR 500 shared 20% samuel, EUR 100
277 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
278 - EUR 300 shared 1/6 [[mnolan]] EUR 50
279 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
280 - EUR 400 shared 25% [[mnolan]] EUR 100
281 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
282 - EUR 150
283
284 ### wishbone 2019-10-043
285
286 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
287 - EUR 500
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
289 - EUR 300
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
291 - EUR 250
292 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
293 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
295 - EUR 300
296 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
297 - EUR 400, 50% shared [[programmerjake]] EUR 200
298 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
299 - EUR 750, 33% shared [[programmerjake]] EUR 250
300 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
301 - EUR 200 50% shared, cole, EUR 100
302 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
303 - EUR 200
304 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
305 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
307 - EUR 150
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
309 - EUR 400 shared 50% [[mnolan]] EUR 200
310 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
311 - EUR 250 shared 40% [[mnolan]] EUR 100
312 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
313 - EUR 300 shared 1/3 [[mnolan]] EUR 100
314 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
315 - EUR 300 shared 50% [[mnolan]] EUR 150
316 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
317 - EUR 750
318 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
319 - EUR 100
320 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
321 - EUR 100
322 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
323 - EUR 100
324 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
325 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
326
327 ### Project 2019-02-012 28-apr-2020
328
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
330 - 6600 scoreboard multi-read/write
331 - EUR 600
332 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
333 - Partitioned equals and greater than comparison
334 - Shared 50% with [[mnolan]]
335 - EUR 200 (each)
336 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
337 - partitioned scalar/vector shift
338 - Shared 50% with [[lkcl]]
339 - EUR 350 (each)
340
341 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
342
343 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
344 - auto-parser of POWER9
345 - Shared 50% with [[mnolan]]
346 - EUR 500 (each)
347
348 ### Project 2019-10-029 Date 14mar2020
349
350 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
351 - EUR 1200
352
353 ### Project 2019-02-012 Date 12mar2020
354
355 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
356 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
357 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
358 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
359
360 ### Project 2019-02-012 Date 28jan2020
361
362 * admin tasks
363 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
364