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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LDST cix
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
22 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
23 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
26 - shared with cole
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
28 - EUR 50, shared with samuel 10%
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
33 - EUR 50, shared with samuel (EUR 350)
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
39 - EUR 400 shared 25% [[mnolan]] EUR 100
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
41 - EUR 500 shared [[mnolan]] samuel, TBD split
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST cache-inhibit
44 - EUR 200
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
46 - EUR 250 (share with cole)
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
52
53 ## Completed but not yet submitted:
54
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LDST sign-extend
56 - EUR 100
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
58 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
60 - EUR 200
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST sign-extend
62 - EUR 100
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
64 - EUR 200
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
66 - EUR 100
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
68 - EUR 200
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
70 - EUR 450
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
72 - EUR 100
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
74
75 donated:
76
77 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
78 - with [[lkcl]]
79 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
81 - functions needed for simulator
82 - Shared 90% with [[lkcl]]
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
84 - Formal proof of decoder
85 - EUR 200
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> parent #195
87 - POWER9 ALU proof
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> parent #195
89 - POWER9 CR proof
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> parent #195
91 - POWER9 BRANCH proof
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> parent #195
93 - POWER9 LOGICAL proof
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> parent #195
95 - POWER9 ROTATE proof
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
97 - MultiCompUnit (and Function Units) proof
98
99 ## Submitted for NLNet RFP
100
101 submitted but not confirmed paid:
102
103 ### Project 2019-02-012 04sep2020 Core
104
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
106 - EUR 2000 total, shared with florent. EUR 1200
107
108 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
109
110 ## Paid
111
112 donation from NLNet confirmed received:
113
114 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
115
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
117 - EUR 2000, python POWER9 simulator
118 - Shared 50% with [[mnolan]], EUR 1000
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
120 - EUR 250, functions needed for simulator
121 - Shared 20% with [[mnolan]], EUR 50
122
123 #### proofs 2019-10-032
124
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
126 - EUR 500 shared 20% samuel, EUR 100
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
128 - EUR 300 shared 1/6 [[mnolan]] EUR 50
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
130 - EUR 400 shared 25% [[mnolan]] EUR 100
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
132 - EUR 150
133
134 ### wishbone 2019-10-043
135
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
137 - EUR 500
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
139 - EUR 300
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
141 - EUR 250
142 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
143 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
145 - EUR 300
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
147 - EUR 400, 50% shared [[programmerjake]] EUR 200
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
149 - EUR 750, 33% shared [[programmerjake]] EUR 250
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
151 - EUR 200 50% shared, cole, EUR 100
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
153 - EUR 200
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
155 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
157 - EUR 150
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
159 - EUR 400 shared 50% [[mnolan]] EUR 200
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
161 - EUR 250 shared 40% [[mnolan]] EUR 100
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
163 - EUR 300 shared 1/3 [[mnolan]] EUR 100
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
165 - EUR 300 shared 50% [[mnolan]] EUR 150
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
167 - EUR 750
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
169 - EUR 100
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
171 - EUR 100
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
173 - EUR 100
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
175 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
176
177 ### Project 2019-02-012 28-apr-2020
178
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
180 - 6600 scoreboard multi-read/write
181 - EUR 600
182 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
183 - Partitioned equals and greater than comparison
184 - Shared 50% with [[mnolan]]
185 - EUR 200 (each)
186 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
187 - partitioned scalar/vector shift
188 - Shared 50% with [[lkcl]]
189 - EUR 350 (each)
190
191 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
192
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
194 - auto-parser of POWER9
195 - Shared 50% with [[mnolan]]
196 - EUR 500 (each)
197
198 ### Project 2019-10-029 Date 14mar2020
199
200 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
201
202 ### Project 2019-02-012 Date 12mar2020
203
204 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
205 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
206 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
207 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
208
209 ### Project 2019-02-012 Date 28jan2020
210
211 * admin tasks
212 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
213