lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  27  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  31    - EUR
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  36  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  37  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  40    - shared with cole
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  42    - EUR 50, shared with samuel 10%
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  47    - EUR 50, shared with samuel (EUR 350)
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  53    - EUR 200
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  56    - donated
  57    - parent #198
  58    - EUR 200
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  60   - MultiCompUnit (and Function Units) proof
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  62   - donated
  63   - parent #195
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  65
  66 ## Completed but not yet submitted:
  67  - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
  68    - EUR 800
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  70  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
  71  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
  72  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  73    - EUR 800 shared between:
  74    - EUR 500 [[lkcl]]
  75    - EUR 300 [[tplaten]]
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
  77    - EUR 5500 shared between:
  78    - EUR 3850 lkcl
  79    - EUR 1650 Others
  80  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
  81    - EUR 1600
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
  83    - EUR 600
  84  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
  85    - EUR 500
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  87  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  89  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  90  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  91
  92
  93  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
  94    - EUR 150
  95    - donated
  96  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
  97    - EUR 200
  98    - donated
  99  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 100    - EUR 150
 101    - donated
 102  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 103    - EUR 200
 104    - donated
 105  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
 106    - EUR 700
 107    - (lip6.fr donated)
 108  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 109    - (total EUR 400 25% donated by LIP6)
 110    - EUR 100 lkcl
 111  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 112    - EUR 900
 113    - shared with [[lxo]]
 114  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 115    - EUR 1100
 116    - shared with lauri, jacob
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 118    - EUR 1250
 119    - Shared 50% with Staf
 120  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 121    - EUR 300
 122    - Shared with Staf, cole
 123  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 124    - EUR 450
 125    - Shared with Staf
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 127  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 128    - EUR 3000
 129    - shared with Staf 50%
 130  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 131    - Project 2019-10-043 06dec2020 wishbone
 132    - EUR (TBD)
 133
 134 ### Project 2019-10-029 14mar2020 coriolis2
 135
 136  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 137    - (total EUR 100 shared 50% with staf)
 138    - EUR 50 lkcl
 139  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 140    - (total EUR 1500 shared 50% with LIP6)
 141    - EUR 750 lkcl
 142  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 143    - (total EUR 400 shared 75% with LIP6)
 144    - EUR 300 lkcl
 145
 146 ### Project 2019-02-012 06dec2020 Core
 147
 148  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 149    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 150  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 151    - EUR 750 donated
 152  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 153    - EUR 1500
 154
 155 ### Project 2019-10-043 06dec2020 wishbone
 156
 157  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 158    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 159  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 160    - EUR 200
 161  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 162    - EUR 100
 163  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 164    - EUR 200
 165  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 166    - EUR 100
 167  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 168    - EUR 200
 169  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 170    - EUR 450
 171  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 172    - EUR 100
 173  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 174    - EUR 200 donated
 175  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 176    - EUR 250 (share with cole)
 177
 178 ### Project 2019-10-032 06dec2020 proofs
 179
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 181    - parent #195
 182    - EUR 400 donated
 183  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 184    - parent #195
 185    - EUR 300 donated
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 187    - EUR 400 donated
 188    - parent #195
 189  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 190    - EUR 400 donated
 191    - parent #195
 192
 193 ## Submitted for NLNet RFP
 194
 195 submitted but not confirmed paid:
 196
 197  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 198
 199 ### Project 2019-02-012 04sep2020 Core
 200
 201  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 202    - EUR 2000 total, shared with florent.  EUR 1200
 203
 204 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 205
 206 ## Paid
 207
 208 donation from NLNet confirmed received:
 209
 210 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 211
 212  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 213     - EUR 2000, python POWER9 simulator
 214     - Shared 50% with [[mnolan]], EUR 1000
 215  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 216     - EUR 250, functions needed for simulator
 217     - Shared 20% with [[mnolan]], EUR 50
 218
 219 ### proofs 2019-10-032
 220
 221  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 222    - EUR 500 shared 20% samuel, EUR 100
 223  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 224    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 225  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 226    - EUR 400 shared 25% [[mnolan]] EUR 100
 227  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 228    - EUR 150
 229
 230 ### wishbone 2019-10-043
 231
 232  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 233    - EUR 500
 234  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 235     - EUR 300
 236  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 237     - EUR 250
 238  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 239    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 240  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 241    - EUR 300
 242  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 243    - EUR 400, 50% shared [[programmerjake]] EUR 200
 244  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 245    - EUR 750, 33% shared [[programmerjake]] EUR 250
 246  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 247    - EUR 200 50% shared, cole, EUR 100
 248  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 249    - EUR 200
 250  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 251    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 252  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 253    - EUR 150
 254  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 255    - EUR 400 shared 50% [[mnolan]] EUR 200
 256  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 257    - EUR 250 shared 40% [[mnolan]] EUR 100
 258  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 259    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 260  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 261    - EUR 300 shared 50% [[mnolan]] EUR 150
 262  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 263    - EUR 750
 264  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 265   - EUR 100
 266  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 267   - EUR 100
 268  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 269    - EUR 100
 270  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 271    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 272
 273 ### Project 2019-02-012 28-apr-2020
 274
 275  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 276    - 6600 scoreboard multi-read/write
 277    - EUR 600
 278  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 279    - Partitioned equals and greater than comparison
 280    - Shared 50% with [[mnolan]]
 281    - EUR 200 (each)
 282  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 283    - partitioned scalar/vector shift
 284    - Shared 50% with [[lkcl]]
 285    - EUR 350 (each)
 286
 287 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 288
 289  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 290     - auto-parser of POWER9
 291     - Shared 50% with [[mnolan]]
 292     - EUR 500 (each)
 293
 294 ### Project 2019-10-029 Date 14mar2020
 295
 296 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 297   - EUR 1200
 298
 299 ### Project 2019-02-012 Date 12mar2020
 300
 301 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 302 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 303 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 304 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 305
 306 ### Project 2019-02-012 Date 28jan2020
 307
 308 * admin tasks
 309 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 310