lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
  19   - EUR 150
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
  21   - EUR 150
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
  25    - EUR 250
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
  27    - EUR 1250
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  37  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  41    - EUR
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  46  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  47  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  50    - shared with cole
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  52    - EUR 50, shared with samuel 10%
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  54
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  57    - EUR 50, shared with samuel (EUR 350)
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  63    - EUR 200
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  65  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  66    - donated
  67    - parent #198
  68    - EUR 200
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  70   - MultiCompUnit (and Function Units) proof
  71  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  72   - donated
  73   - parent #195
  74  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  75
  76 ## Completed but not yet submitted:
  77
  78 TO SORT
  79
  80 28feb2022
  81
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
  83    * EUR 1500 (shared with [[tplaten]])
  84  - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
  85    * EUR 1500 (shared with [[tplaten]])
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
  87    * EUR 1000 (shared with [[tplaten]])
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
  89    * EUR 500 (shared with [[programmerjake]])
  90  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  91    * EUR 400 (shared with [[programmerjake]])
  92
  93 before that
  94
  95  - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
  96    - EUR 1600
  97    - EUR 800 shared with [[klehman]]
  98    - EUR 800 shared with [[lkcl]]
  99  - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
 100    - EUR 800
 101  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
 102  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
 104  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
 105    - EUR 500
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
 108  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
 111
 112
 113  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 114    - EUR 150
 115    - donated
 116  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 117    - EUR 200
 118    - donated
 119  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 120    - EUR 150
 121    - donated
 122  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 123    - EUR 200
 124    - donated
 125  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
 126    - EUR 700
 127    - (lip6.fr donated)
 128  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 129    - (total EUR 400 25% donated by LIP6)
 130    - EUR 100 lkcl
 131  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 132    - EUR 900
 133    - shared with [[lxo]]
 134  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 135    - EUR 1100
 136    - shared with lauri, jacob
 137  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 138    - EUR 1250
 139    - Shared 50% with Staf
 140  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 141    - EUR 300
 142    - Shared with Staf, cole
 143  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 144    - EUR 450
 145    - Shared with Staf
 146  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 147  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 148    - Project 2019-10-043 06dec2020 wishbone
 149    - EUR (TBD)
 150
 151 ### Project 2019-10-029 14mar2020 coriolis2
 152
 153  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 154    - (total EUR 100 shared 50% with staf)
 155    - EUR 50 lkcl
 156  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 157    - (total EUR 1500 shared 50% with LIP6)
 158    - EUR 750 lkcl
 159  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 160    - (total EUR 400 shared 75% with LIP6)
 161    - EUR 300 lkcl
 162
 163 ### Project 2019-02-012 06dec2020 Core
 164
 165  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 166    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 167  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 168    - EUR 750 donated
 169  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 170    - EUR 1500
 171
 172 ### Project 2019-10-043 06dec2020 wishbone
 173
 174  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 175    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 176  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 177    - EUR 200
 178  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 179    - EUR 100
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 181    - EUR 200
 182  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 183    - EUR 100
 184  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 185    - EUR 200
 186  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 187    - EUR 450
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 189    - EUR 100
 190  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 191    - EUR 200 donated
 192  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 193    - EUR 250 (share with cole)
 194
 195 ### Project 2019-10-032 06dec2020 proofs
 196
 197  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 198    - parent #195
 199    - EUR 400 donated
 200  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 201    - parent #195
 202    - EUR 300 donated
 203  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 204    - EUR 400 donated
 205    - parent #195
 206  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 207    - EUR 400 donated
 208    - parent #195
 209
 210 ## Submitted for NLNet RFP
 211
 212 submitted 2021-dec-09 but not confirmed paid
 213
 214  - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
 215    - EUR 300
 216  - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
 217    - EUR 250
 218  - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
 219  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
 220  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
 221    - EUR 800 shared between:
 222    - EUR 500 [[lkcl]]
 223    - EUR 300 [[tplaten]]
 224  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
 225    - EUR 5500 shared between:
 226    - EUR 3850 lkcl
 227    - EUR 1650 Others
 228  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
 229    - EUR 1600
 230  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
 231    - EUR 600
 232  - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
 233    - EUR 500 shared between:
 234    - EUR 100 [[lkcl]]
 235    - EUR 325 dmitry
 236    - EUR 75 maciej
 237  - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
 238
 239
 240 ### Project 2019-02-012 04sep2020 Core
 241
 242  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 243    - EUR 2000 total, shared with florent.  EUR 1200
 244
 245 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 246
 247 ## Paid
 248
 249 donation from NLNet confirmed received:
 250
 251 ### coriolis2 2021-apr-04
 252
 253  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 254    - EUR 3000
 255    - shared with Staf 50%
 256
 257 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 258
 259  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 260     - EUR 2000, python POWER9 simulator
 261     - Shared 50% with [[mnolan]], EUR 1000
 262  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 263     - EUR 250, functions needed for simulator
 264     - Shared 20% with [[mnolan]], EUR 50
 265
 266 ### proofs 2019-10-032
 267
 268  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 269    - EUR 500 shared 20% samuel, EUR 100
 270  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 271    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 272  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 273    - EUR 400 shared 25% [[mnolan]] EUR 100
 274  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 275    - EUR 150
 276
 277 ### wishbone 2019-10-043
 278
 279  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 280    - EUR 500
 281  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 282     - EUR 300
 283  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 284     - EUR 250
 285  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 286    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 287  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 288    - EUR 300
 289  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 290    - EUR 400, 50% shared [[programmerjake]] EUR 200
 291  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 292    - EUR 750, 33% shared [[programmerjake]] EUR 250
 293  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 294    - EUR 200 50% shared, cole, EUR 100
 295  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 296    - EUR 200
 297  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 298    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 299  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 300    - EUR 150
 301  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 302    - EUR 400 shared 50% [[mnolan]] EUR 200
 303  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 304    - EUR 250 shared 40% [[mnolan]] EUR 100
 305  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 306    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 307  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 308    - EUR 300 shared 50% [[mnolan]] EUR 150
 309  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 310    - EUR 750
 311  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 312   - EUR 100
 313  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 314   - EUR 100
 315  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 316    - EUR 100
 317  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 318    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 319
 320 ### Project 2019-02-012 28-apr-2020
 321
 322  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 323    - 6600 scoreboard multi-read/write
 324    - EUR 600
 325  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 326    - Partitioned equals and greater than comparison
 327    - Shared 50% with [[mnolan]]
 328    - EUR 200 (each)
 329  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 330    - partitioned scalar/vector shift
 331    - Shared 50% with [[lkcl]]
 332    - EUR 350 (each)
 333
 334 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 335
 336  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 337     - auto-parser of POWER9
 338     - Shared 50% with [[mnolan]]
 339     - EUR 500 (each)
 340
 341 ### Project 2019-10-029 Date 14mar2020
 342
 343 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 344   - EUR 1200
 345
 346 ### Project 2019-02-012 Date 12mar2020
 347
 348 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 349 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 350 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 351 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 352
 353 ### Project 2019-02-012 Date 28jan2020
 354
 355 * admin tasks
 356 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 357