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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcodes
16 - EUR
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
26 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
27 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
30 - shared with cole
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
32 - EUR 50, shared with samuel 10%
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
37 - EUR 50, shared with samuel (EUR 350)
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
44 - EUR 200
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
51 - donated
52 - parent #198
53 - EUR 200
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
55 - MultiCompUnit (and Function Units) proof
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
57 - donated
58 - parent #195
59
60 ## Completed but not yet submitted:
61
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
63 - Project 2019-10-043 06dec2020 wishbone
64 - EUR 0 (TBD)
65
66 ### Project 2019-10-029 14mar2020 coriolis2
67
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
69 - (total EUR 100 shared 50% with staf)
70 - EUR 50 lkcl
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
72 - (total EUR 1500 shared 50% with LIP6)
73 - EUR 750 lkcl
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
75 - (total EUR 400 shared 75% with LIP6)
76 - EUR 300 lkcl
77
78 ### Project 2019-02-012 06dec2020 Core
79
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
81 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
82 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
83 - EUR 750 donated
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
85 - EUR 1500
86
87 ### Project 2019-10-043 06dec2020 wishbone
88
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
90 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
92 - EUR 200
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
94 - EUR 100
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
96 - EUR 200
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
98 - EUR 100
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
100 - EUR 200
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
102 - EUR 450
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
104 - EUR 100
105 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
106 - EUR 200 donated
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
108 - EUR 250 (share with cole)
109
110 ### Project 2019-10-032 06dec2020 proofs
111
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
113 - parent #195
114 - EUR 400 donated
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
116 - parent #195
117 - EUR 300 donated
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
119 - EUR 400 donated
120 - parent #195
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
122 - EUR 400 donated
123 - parent #195
124
125 ## Submitted for NLNet RFP
126
127 submitted but not confirmed paid:
128
129 ### Project 2019-02-012 04sep2020 Core
130
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
132 - EUR 2000 total, shared with florent. EUR 1200
133
134 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
135
136 ## Paid
137
138 donation from NLNet confirmed received:
139
140 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
141
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
143 - EUR 2000, python POWER9 simulator
144 - Shared 50% with [[mnolan]], EUR 1000
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
146 - EUR 250, functions needed for simulator
147 - Shared 20% with [[mnolan]], EUR 50
148
149 ### proofs 2019-10-032
150
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
152 - EUR 500 shared 20% samuel, EUR 100
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
154 - EUR 300 shared 1/6 [[mnolan]] EUR 50
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
156 - EUR 400 shared 25% [[mnolan]] EUR 100
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
158 - EUR 150
159
160 ### wishbone 2019-10-043
161
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
163 - EUR 500
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
165 - EUR 300
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
167 - EUR 250
168 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
169 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
171 - EUR 300
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
173 - EUR 400, 50% shared [[programmerjake]] EUR 200
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
175 - EUR 750, 33% shared [[programmerjake]] EUR 250
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
177 - EUR 200 50% shared, cole, EUR 100
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
179 - EUR 200
180 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
181 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
183 - EUR 150
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
185 - EUR 400 shared 50% [[mnolan]] EUR 200
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
187 - EUR 250 shared 40% [[mnolan]] EUR 100
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
189 - EUR 300 shared 1/3 [[mnolan]] EUR 100
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
191 - EUR 300 shared 50% [[mnolan]] EUR 150
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
193 - EUR 750
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
195 - EUR 100
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
197 - EUR 100
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
199 - EUR 100
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
201 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
202
203 ### Project 2019-02-012 28-apr-2020
204
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
206 - 6600 scoreboard multi-read/write
207 - EUR 600
208 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
209 - Partitioned equals and greater than comparison
210 - Shared 50% with [[mnolan]]
211 - EUR 200 (each)
212 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
213 - partitioned scalar/vector shift
214 - Shared 50% with [[lkcl]]
215 - EUR 350 (each)
216
217 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
218
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
220 - auto-parser of POWER9
221 - Shared 50% with [[mnolan]]
222 - EUR 500 (each)
223
224 ### Project 2019-10-029 Date 14mar2020
225
226 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
227 - EUR 1200
228
229 ### Project 2019-02-012 Date 12mar2020
230
231 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
232 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
233 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
234 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
235
236 ### Project 2019-02-012 Date 28jan2020
237
238 * admin tasks
239 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
240