lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8
   9 # Status tracking
  10
  11 move things along from one stage to the next
  12
  13 ## Currently working on
  14
  15  - Project Management
  16  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  23  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  27    - EUR
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  36  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  37  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  40    - shared with cole
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  42    - EUR 50, shared with samuel 10%
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  47    - EUR 50, shared with samuel (EUR 350)
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  54    - EUR 200
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  61    - donated
  62    - parent #198
  63    - EUR 200
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  65   - MultiCompUnit (and Function Units) proof
  66  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  67   - donated
  68   - parent #195
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  70
  71 ## Completed but not yet submitted:
  72
  73  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
  74    - EUR 150
  75    - donated
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
  77    - EUR 200
  78    - donated
  79  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
  80    - EUR 150
  81    - donated
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
  83    - EUR 200
  84    - donated
  85  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
  86    - EUR 700
  87    - (lip6.fr donated)
  88  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  89    - (total EUR 400 25% donated by LIP6)
  90    - EUR 100 lkcl
  91  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  92    - EUR 900
  93    - shared with [[lxo]]
  94  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
  95    - EUR 1100
  96    - shared with lauri, jacob
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
  98    - EUR 1250
  99    - Shared 50% with Staf
 100  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 101    - EUR 300
 102    - Shared with Staf, cole
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 104    - EUR 450
 105    - Shared with Staf
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 108    - EUR 3000
 109    - shared with Staf 50%
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 111    - Project 2019-10-043 06dec2020 wishbone
 112    - EUR (TBD)
 113
 114 ### Project 2019-10-029 14mar2020 coriolis2
 115
 116  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 117    - (total EUR 100 shared 50% with staf)
 118    - EUR 50 lkcl
 119  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 120    - (total EUR 1500 shared 50% with LIP6)
 121    - EUR 750 lkcl
 122  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 123    - (total EUR 400 shared 75% with LIP6)
 124    - EUR 300 lkcl
 125
 126 ### Project 2019-02-012 06dec2020 Core
 127
 128  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 129    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 130  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 131    - EUR 750 donated
 132  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 133    - EUR 1500
 134
 135 ### Project 2019-10-043 06dec2020 wishbone
 136
 137  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 138    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 139  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 140    - EUR 200
 141  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 142    - EUR 100
 143  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 144    - EUR 200
 145  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 146    - EUR 100
 147  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 148    - EUR 200
 149  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 150    - EUR 450
 151  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 152    - EUR 100
 153  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 154    - EUR 200 donated
 155  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 156    - EUR 250 (share with cole)
 157
 158 ### Project 2019-10-032 06dec2020 proofs
 159
 160  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 161    - parent #195
 162    - EUR 400 donated
 163  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 164    - parent #195
 165    - EUR 300 donated
 166  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 167    - EUR 400 donated
 168    - parent #195
 169  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 170    - EUR 400 donated
 171    - parent #195
 172
 173 ## Submitted for NLNet RFP
 174
 175 submitted but not confirmed paid:
 176
 177 ### Project 2019-02-012 04sep2020 Core
 178
 179  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 180    - EUR 2000 total, shared with florent.  EUR 1200
 181
 182 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 183
 184 ## Paid
 185
 186 donation from NLNet confirmed received:
 187
 188 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 189
 190  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 191     - EUR 2000, python POWER9 simulator
 192     - Shared 50% with [[mnolan]], EUR 1000
 193  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 194     - EUR 250, functions needed for simulator
 195     - Shared 20% with [[mnolan]], EUR 50
 196
 197 ### proofs 2019-10-032
 198
 199  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 200    - EUR 500 shared 20% samuel, EUR 100
 201  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 202    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 203  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 204    - EUR 400 shared 25% [[mnolan]] EUR 100
 205  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 206    - EUR 150
 207
 208 ### wishbone 2019-10-043
 209
 210  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 211    - EUR 500
 212  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 213     - EUR 300
 214  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 215     - EUR 250
 216  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 217    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 218  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 219    - EUR 300
 220  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 221    - EUR 400, 50% shared [[programmerjake]] EUR 200
 222  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 223    - EUR 750, 33% shared [[programmerjake]] EUR 250
 224  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 225    - EUR 200 50% shared, cole, EUR 100
 226  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 227    - EUR 200
 228  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 229    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 230  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 231    - EUR 150
 232  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 233    - EUR 400 shared 50% [[mnolan]] EUR 200
 234  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 235    - EUR 250 shared 40% [[mnolan]] EUR 100
 236  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 237    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 238  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 239    - EUR 300 shared 50% [[mnolan]] EUR 150
 240  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 241    - EUR 750
 242  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 243   - EUR 100
 244  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 245   - EUR 100
 246  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 247    - EUR 100
 248  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 249    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 250
 251 ### Project 2019-02-012 28-apr-2020
 252
 253  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 254    - 6600 scoreboard multi-read/write
 255    - EUR 600
 256  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 257    - Partitioned equals and greater than comparison
 258    - Shared 50% with [[mnolan]]
 259    - EUR 200 (each)
 260  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 261    - partitioned scalar/vector shift
 262    - Shared 50% with [[lkcl]]
 263    - EUR 350 (each)
 264
 265 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 266
 267  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 268     - auto-parser of POWER9
 269     - Shared 50% with [[mnolan]]
 270     - EUR 500 (each)
 271
 272 ### Project 2019-10-029 Date 14mar2020
 273
 274 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 275   - EUR 1200
 276
 277 ### Project 2019-02-012 Date 12mar2020
 278
 279 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 280 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 281 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 282 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 283
 284 ### Project 2019-02-012 Date 28jan2020
 285
 286 * admin tasks
 287 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 288