1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
31 - https://bugs.libre-soc.org/show_bug.cgi?id=575
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
40 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
41 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
46 - EUR 50, shared with samuel 10%
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
51 - EUR 50, shared with samuel (EUR 350)
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
64 - MultiCompUnit (and Function Units) proof
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
70 ## Completed but not yet submitted:
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
76 - EUR 800 shared with [[klehman]]
77 - EUR 800 shared with [[lkcl]]
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
104 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
108 - (total EUR 400 25% donated by LIP6)
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
112 - shared with [[lxo]]
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
115 - shared with lauri, jacob
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
118 - Shared 50% with Staf
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
121 - Shared with Staf, cole
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
128 - shared with Staf 50%
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
130 - Project 2019-10-043 06dec2020 wishbone
133 ### Project 2019-10-029 14mar2020 coriolis2
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
136 - (total EUR 100 shared 50% with staf)
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
139 - (total EUR 1500 shared 50% with LIP6)
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
142 - (total EUR 400 shared 75% with LIP6)
145 ### Project 2019-02-012 06dec2020 Core
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
148 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
149 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
154 ### Project 2019-10-043 06dec2020 wishbone
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
157 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
172 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
175 - EUR 250 (share with cole)
177 ### Project 2019-10-032 06dec2020 proofs
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
192 ## Submitted for NLNet RFP
194 submitted but not confirmed paid:
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
198 submitted 2021-dec-09 but not confirmed paid
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
207 - EUR 800 shared between:
209 - EUR 300 [[tplaten]]
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
211 - EUR 5500 shared between:
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
219 - EUR 500 shared between:
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
226 ### Project 2019-02-012 04sep2020 Core
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
229 - EUR 2000 total, shared with florent. EUR 1200
231 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
235 donation from NLNet confirmed received:
237 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
240 - EUR 2000, python POWER9 simulator
241 - Shared 50% with [[mnolan]], EUR 1000
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
243 - EUR 250, functions needed for simulator
244 - Shared 20% with [[mnolan]], EUR 50
246 ### proofs 2019-10-032
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
249 - EUR 500 shared 20% samuel, EUR 100
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
251 - EUR 300 shared 1/6 [[mnolan]] EUR 50
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
253 - EUR 400 shared 25% [[mnolan]] EUR 100
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
257 ### wishbone 2019-10-043
259 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
261 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
265 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
266 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
270 - EUR 400, 50% shared [[programmerjake]] EUR 200
271 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
272 - EUR 750, 33% shared [[programmerjake]] EUR 250
273 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
274 - EUR 200 50% shared, cole, EUR 100
275 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
277 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
278 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
279 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
281 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
282 - EUR 400 shared 50% [[mnolan]] EUR 200
283 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
284 - EUR 250 shared 40% [[mnolan]] EUR 100
285 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
286 - EUR 300 shared 1/3 [[mnolan]] EUR 100
287 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
288 - EUR 300 shared 50% [[mnolan]] EUR 150
289 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
291 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
293 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
298 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
300 ### Project 2019-02-012 28-apr-2020
302 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
303 - 6600 scoreboard multi-read/write
305 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
306 - Partitioned equals and greater than comparison
307 - Shared 50% with [[mnolan]]
309 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
310 - partitioned scalar/vector shift
311 - Shared 50% with [[lkcl]]
314 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
316 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
317 - auto-parser of POWER9
318 - Shared 50% with [[mnolan]]
321 ### Project 2019-10-029 Date 14mar2020
323 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
326 ### Project 2019-02-012 Date 12mar2020
328 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
329 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
330 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
331 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
333 ### Project 2019-02-012 Date 28jan2020
336 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>