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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcodes
17 - EUR
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
27 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
28 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
31 - shared with cole
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
33 - EUR 50, shared with samuel 10%
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
38 - EUR 50, shared with samuel (EUR 350)
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
45 - EUR 200
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
52 - donated
53 - parent #198
54 - EUR 200
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
56 - MultiCompUnit (and Function Units) proof
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
58 - donated
59 - parent #195
60
61 ## Completed but not yet submitted:
62
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
64 - Project 2019-10-043 06dec2020 wishbone
65 - EUR 0 (TBD)
66
67 ### Project 2019-10-029 14mar2020 coriolis2
68
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
70 - (total EUR 100 shared 50% with staf)
71 - EUR 50 lkcl
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
73 - (total EUR 1500 shared 50% with LIP6)
74 - EUR 750 lkcl
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
76 - (total EUR 400 shared 75% with LIP6)
77 - EUR 300 lkcl
78
79 ### Project 2019-02-012 06dec2020 Core
80
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
82 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
83 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
84 - EUR 750 donated
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
86 - EUR 1500
87
88 ### Project 2019-10-043 06dec2020 wishbone
89
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
91 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
93 - EUR 200
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
95 - EUR 100
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
97 - EUR 200
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
99 - EUR 100
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
101 - EUR 200
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
103 - EUR 450
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
105 - EUR 100
106 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
107 - EUR 200 donated
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
109 - EUR 250 (share with cole)
110
111 ### Project 2019-10-032 06dec2020 proofs
112
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
114 - parent #195
115 - EUR 400 donated
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
117 - parent #195
118 - EUR 300 donated
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
120 - EUR 400 donated
121 - parent #195
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
123 - EUR 400 donated
124 - parent #195
125
126 ## Submitted for NLNet RFP
127
128 submitted but not confirmed paid:
129
130 ### Project 2019-02-012 04sep2020 Core
131
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
133 - EUR 2000 total, shared with florent. EUR 1200
134
135 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
136
137 ## Paid
138
139 donation from NLNet confirmed received:
140
141 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
142
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
144 - EUR 2000, python POWER9 simulator
145 - Shared 50% with [[mnolan]], EUR 1000
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
147 - EUR 250, functions needed for simulator
148 - Shared 20% with [[mnolan]], EUR 50
149
150 ### proofs 2019-10-032
151
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
153 - EUR 500 shared 20% samuel, EUR 100
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
155 - EUR 300 shared 1/6 [[mnolan]] EUR 50
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
157 - EUR 400 shared 25% [[mnolan]] EUR 100
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
159 - EUR 150
160
161 ### wishbone 2019-10-043
162
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
164 - EUR 500
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
166 - EUR 300
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
168 - EUR 250
169 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
170 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
172 - EUR 300
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
174 - EUR 400, 50% shared [[programmerjake]] EUR 200
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
176 - EUR 750, 33% shared [[programmerjake]] EUR 250
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
178 - EUR 200 50% shared, cole, EUR 100
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
180 - EUR 200
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
182 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
184 - EUR 150
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
186 - EUR 400 shared 50% [[mnolan]] EUR 200
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
188 - EUR 250 shared 40% [[mnolan]] EUR 100
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
190 - EUR 300 shared 1/3 [[mnolan]] EUR 100
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
192 - EUR 300 shared 50% [[mnolan]] EUR 150
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
194 - EUR 750
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
196 - EUR 100
197 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
198 - EUR 100
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
200 - EUR 100
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
202 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
203
204 ### Project 2019-02-012 28-apr-2020
205
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
207 - 6600 scoreboard multi-read/write
208 - EUR 600
209 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
210 - Partitioned equals and greater than comparison
211 - Shared 50% with [[mnolan]]
212 - EUR 200 (each)
213 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
214 - partitioned scalar/vector shift
215 - Shared 50% with [[lkcl]]
216 - EUR 350 (each)
217
218 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
219
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
221 - auto-parser of POWER9
222 - Shared 50% with [[mnolan]]
223 - EUR 500 (each)
224
225 ### Project 2019-10-029 Date 14mar2020
226
227 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
228 - EUR 1200
229
230 ### Project 2019-02-012 Date 12mar2020
231
232 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
233 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
234 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
235 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
236
237 ### Project 2019-02-012 Date 28jan2020
238
239 * admin tasks
240 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
241