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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8
9 # Status tracking
10
11 move things along from one stage to the next
12
13 ## Currently working on
14
15 - Project Management
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
18 - https://bugs.libre-soc.org/show_bug.cgi?id=575
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
22 - EUR
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
31 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
32 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
35 - shared with cole
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
37 - EUR 50, shared with samuel 10%
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
42 - EUR 50, shared with samuel (EUR 350)
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
49 - EUR 200
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
56 - donated
57 - parent #198
58 - EUR 200
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
60 - MultiCompUnit (and Function Units) proof
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
62 - donated
63 - parent #195
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
65
66 ## Completed but not yet submitted:
67
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
69 - EUR 150
70 - donated
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
72 - EUR 200
73 - donated
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
75 - EUR 150
76 - donated
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
78 - EUR 200
79 - donated
80 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
81 - EUR 700
82 - (lip6.fr donated)
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
84 - (total EUR 400 25% donated by LIP6)
85 - EUR 100 lkcl
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
87 - EUR 900
88 - shared with [[lxo]]
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
90 - EUR 1100
91 - shared with lauri, jacob
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
93 - EUR 1250
94 - Shared 50% with Staf
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
96 - EUR 300
97 - Shared with Staf, cole
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
99 - EUR 450
100 - Shared with Staf
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
103 - EUR 3000
104 - shared with Staf 50%
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
106 - Project 2019-10-043 06dec2020 wishbone
107 - EUR (TBD)
108
109 ### Project 2019-10-029 14mar2020 coriolis2
110
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
112 - (total EUR 100 shared 50% with staf)
113 - EUR 50 lkcl
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
115 - (total EUR 1500 shared 50% with LIP6)
116 - EUR 750 lkcl
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
118 - (total EUR 400 shared 75% with LIP6)
119 - EUR 300 lkcl
120
121 ### Project 2019-02-012 06dec2020 Core
122
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
124 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
125 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
126 - EUR 750 donated
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
128 - EUR 1500
129
130 ### Project 2019-10-043 06dec2020 wishbone
131
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
133 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
135 - EUR 200
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
137 - EUR 100
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
139 - EUR 200
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
141 - EUR 100
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
143 - EUR 200
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
145 - EUR 450
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
147 - EUR 100
148 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
149 - EUR 200 donated
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
151 - EUR 250 (share with cole)
152
153 ### Project 2019-10-032 06dec2020 proofs
154
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
156 - parent #195
157 - EUR 400 donated
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
159 - parent #195
160 - EUR 300 donated
161 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
162 - EUR 400 donated
163 - parent #195
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
165 - EUR 400 donated
166 - parent #195
167
168 ## Submitted for NLNet RFP
169
170 submitted but not confirmed paid:
171
172 ### Project 2019-02-012 04sep2020 Core
173
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
175 - EUR 2000 total, shared with florent. EUR 1200
176
177 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
178
179 ## Paid
180
181 donation from NLNet confirmed received:
182
183 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
184
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
186 - EUR 2000, python POWER9 simulator
187 - Shared 50% with [[mnolan]], EUR 1000
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
189 - EUR 250, functions needed for simulator
190 - Shared 20% with [[mnolan]], EUR 50
191
192 ### proofs 2019-10-032
193
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
195 - EUR 500 shared 20% samuel, EUR 100
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
197 - EUR 300 shared 1/6 [[mnolan]] EUR 50
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
199 - EUR 400 shared 25% [[mnolan]] EUR 100
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
201 - EUR 150
202
203 ### wishbone 2019-10-043
204
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
206 - EUR 500
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
208 - EUR 300
209 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
210 - EUR 250
211 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
212 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
214 - EUR 300
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
216 - EUR 400, 50% shared [[programmerjake]] EUR 200
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
218 - EUR 750, 33% shared [[programmerjake]] EUR 250
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
220 - EUR 200 50% shared, cole, EUR 100
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
222 - EUR 200
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
224 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
226 - EUR 150
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
228 - EUR 400 shared 50% [[mnolan]] EUR 200
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
230 - EUR 250 shared 40% [[mnolan]] EUR 100
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
232 - EUR 300 shared 1/3 [[mnolan]] EUR 100
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
234 - EUR 300 shared 50% [[mnolan]] EUR 150
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
236 - EUR 750
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
238 - EUR 100
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
240 - EUR 100
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
242 - EUR 100
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
244 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
245
246 ### Project 2019-02-012 28-apr-2020
247
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
249 - 6600 scoreboard multi-read/write
250 - EUR 600
251 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
252 - Partitioned equals and greater than comparison
253 - Shared 50% with [[mnolan]]
254 - EUR 200 (each)
255 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
256 - partitioned scalar/vector shift
257 - Shared 50% with [[lkcl]]
258 - EUR 350 (each)
259
260 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
261
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
263 - auto-parser of POWER9
264 - Shared 50% with [[mnolan]]
265 - EUR 500 (each)
266
267 ### Project 2019-10-029 Date 14mar2020
268
269 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
270 - EUR 1200
271
272 ### Project 2019-02-012 Date 12mar2020
273
274 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
275 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
276 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
277 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
278
279 ### Project 2019-02-012 Date 28jan2020
280
281 * admin tasks
282 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
283