llvm_vector_backend.mdwn

   1 # LLVM Backend Array Register Files
   2
   3 # Data Structures
   4
   5 ## Array Register File
   6
   7 This is for being able to express remapping / retargetting / redirection
   8 schemes that a microarchitecture has.
   9
  10     typedef struct {
  11         start: 12; // starting index of the "register"
  12         end: 12; // ending index of the "register" (inclusive)
  13         id: 8; // type of register: e.g 0=float, 1=int, 2=...
  14     } ARF;
  15
  16 Examples:
  17
  18     ARF1 = 0x01009005
  19     ARF2 = 0x0100a006
  20     ARF3 = 0x0100b008
  21
  22 These would indicate that when the (virtual) register ARF1 is used,
  23 it is of type "integer", and it requires the reservation of the **real**
  24 registers 5 through 9 at the hardware level.
  25
  26 ## Base Register Class
  27
  28     typedef struct {
  29         ARF: arf;  // the Array Register File identifier
  30         min: 12;   // if an opcode restricts the available range, use this
  31         max: 12;   // ... and this
  32         size: 8;   // the element bitwidth. e.g. 0=8, 1=16, 2=32.. TBD
  33         align: 4;  // an aligment restriction, in powers of 2.
  34     } BRC;
  35
  36 Examples:
  37
  38     A Compressed instruction from SV has restrictions on the
  39     range it may cover (unless redirection is taken into account).
  40     It is also possible to specify a bitwidth of 16, and if that is
  41     done, alignment has to be restricted to 4.  So:
  42
  43     brc1 = {
  44         arf = 0x0100b008; // integer register, using "real" regs 8-11 inclusive
  45         min = 8;          // C-type instructions go from 8-15 in the opcode
  46         max = 15;
  47         size = 0x1        // 1=16-bit (?)
  48         align: 2          // 2= 1<<2 (=4) because the "real" regs are 64-bit.
  49     };
  50
  51 ## Register Class Unions
  52
  53 Register Classes are the union of multiple Base Register Classes
  54 and traditional register classes.  In this way, all possible meanings
  55 and uses to which registers may be put can be expressed in one structure.
  56
  57 # Examples per Implementor
  58
  59 ## Array Register File
  60
  61 ### SimpleV
  62
  63 ### RVV
  64
  65 ### AMDGPU
  66
  67 ## Base Register Class
  68
  69 ### SimpleV
  70
  71 ### RVV
  72
  73 ### AMDGPU
  74
  75 ## Register Class Unions
  76
  77 ### SimpleV
  78
  79 ### RVV
  80
  81 ### AMDGPU
  82