meetings/dmitry_2023-11-24.mdwn

   1 # Friday 24th November 17:00 UTC
   2
   3 - A meeting with Dmitry, David, James, Luke, and Andrey to explain the
   4 new grants for updating Simple-V for RISC-V (first implemented 4 years
   5 ago, now in need of an update)
   6
   7 Main points to take away:
   8
   9 - There will be two new grants (links below).
  10 - Meeting on Tuesday will be used for planning the binutils grant.
  11 Link to next week's meeting: [[meetings/sync_up/sync_up_2023-11-28]]
  12
  13 ## New SV Expansion Grant
  14
  15 - [[nlnet_2023_simplev_riscv]]
  16
  17 The expansion grant. Primary focus on:
  18
  19 - Add RISC-V ISA support to ISACAller.
  20 - Extend `svanalysis.py` for characterising RISC-V instructions
  21 (number of reg ports, insn type, etc.). Link to existing
  22 [svanalysis.py](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;h=21778ad02d78c4f7ef5b6df93e096f4abbe365ad;hb=HEAD)
  23 - Extending existing sv for of the RISC-V Spike sim to support
  24 full feature set of SimpleV. Link to LibreSOC'
  25 [sv spike repo](https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv)
  26
  27 ## New Binutils Grant
  28
  29 - [[nlnet_2023_simplev_riscv_binutils]]
  30
  31 - Primarily Dmitry doing most of the work.
  32 - Communication on Simple-V formats to be defined by luke and jacob
  33
  34 ## Primary Tasks
  35
  36   1. Finish writing libopid, some of the work started 4 months ago
  37 (no RfPs can be submitted for that work). Link to
  38 [repo](https://git.libre-soc.org/?p=mdis.git;a=summary)
  39   2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid
  40    (without losing CSV files which are machine-readable by other projects)
  41   3. Create RISC-V instruction database using libopid.
  42   4. Implement SVP64 PowerISA in libopid.
  43   5. Implement SimpleV for RISC-V in libopid.
  44      - SVP32 (16+16) - 16-bit prefix for 16-bit compressed instructions.
  45      - SVP48 (16+32) - 16-bit prefix for 32-bit instructions.
  46      - SVP64 (32+32) - 32-bit prefix for 64-bit instructions.
  47
  48 * The 16-bit prefix saves instruction space in memory
  49  (but with limited feature set: 128 regs span but cruder spacing).
  50 * The 32-bit prefix gives full access to SimpleV feature set
  51  (128 regs, all SV modes such as data dependent fail-first, etc.)
  52
  53 # Defining SVPxxSingle
  54
  55 Another point mentioned after Dmitry left is the need to define SVPxxSingle.
  56 [[openpower/sv/svp64-single]]
  57
  58 For both RISC-V and PowerISA need to define:
  59
  60 - SVP16Single
  61 - SVP32Single
  62 - SVP64Single
  63
  64 *(Andrey: Why do these need to be defined for PowerISA?
  65 A: see page and bugreport. full 128 reg access)*
  66
  67 Doing this work for both ISAs at the same time isn't too difficult,
  68 as the SVPxxSingle format will be the same for both ISAs.
  69 By defining SV format to be the same across ISAs saves effort
  70 and helps future programmers to switch from one ISA to another
  71 with minimal adjustment...*perhaps except for x86*...)
  72
  73 [[!tag meeting2023]]
  74