meetings/sync_up/sync_up_2023-12-05.mdwn

   1 # Tuesday 5th December 17:00 UTC
   2
   3 * Previous week's notes: [[meetings/sync_up/sync_up_2023-11-28]]
   4 * Next day's notes: [[meetings/sync_up/sync_up_2023-12-06]]
   5 * Next week's notes: [[meetings/sync_up/sync_up_2023-12-12]]
   6
   7 **TODO EDIT, this is a clone/copy of last weeks notes (easier, saves time)**
   8
   9 # Main Agenda
  10
  11 * reminder of **only 12 weeks** until march 1st deadline
  12   for completion of cavatools and cryptoprimitives.
  13
  14 Meeting notes:
  15
  16 - Deprecated SimpleV prefix format from 2019: <https://libre-soc.org/simple_v_extension/sv_prefix_proposal/>
  17 - RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
  18 - The first step is to make modifications to `sv_analysis.py` to classify the RISC-V instructions.
  19   <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>
  20 - Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
  21
  22 - [bug #980](https://bugs.libre-soc.org/show_bug.cgi?id=980)
  23   - A lot of work, need to focus on the basics
  24   - Issues with current Python pseudo-code compiler:
  25     - pseudocode is full of python-isms such as some variables are
  26     python ints and some are selectableint and some are strings etc.
  27     - plus, the parser currently has wrong operator precedence
  28     [bug #1082](https://bugs.libre-soc.org/show_bug.cgi?id=1082).
  29   - Suggested minimal goal for bug #980 is:
  30     - Use AST (operands, flow, etc. as we already do for generated
  31     Python func's) and a custom visitor function to convert to C code.
  32     - Generate C functions which can be compiled without errors.
  33     - Generated functions can be run from a main function to confirm results.
  34     - Jacob suggested using `maddedu` as a benchmark, since it has
  35     non-trivial pseudo-code.
  36     -
  37
  38
  39 # Dmitry
  40
  41 * Update [bug #1126](https://bugs.libre-soc.org/show_bug.cgi?id=1126)
  42 to include git commit descriptions.
  43 * Check whether RISC-V have their own way of describing the instructions
  44   (likely they do).
  45 * Familiarise yourself with
  46 [svanalysis.py](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;h=21778ad02d78c4f7ef5b6df93e096f4abbe365ad;hb=HEAD),
  47 as we will need a similar tool for RISC-V.
  48 * Check what RISC-V support in binutils looks like. *Needed for confirming
  49 the details of the RISC-V binutils grant*.
  50
  51 # Sadoon
  52
  53 - Work together with Shriya (with Luke's asssitance) on Poly1305/ED25519.
  54 - Submitted talk proposals for FOSDEM 2024
  55
  56 # Jacob
  57
  58 - [bug #1169](https://bugs.libre-soc.org/show_bug.cgi?id=1169)
  59 Completed the necessary bits of mmap for ELF task.
  60
  61 # David
  62
  63 -
  64
  65 # Andrey
  66
  67 - Check with Dmitry on git commit descriptions (bug #1126).
  68 Once comment made, add to [[HDL_workflow]] documentation.
  69
  70 # Luke
  71
  72 * [bug #672](https://bugs.libre-soc.org/show_bug.cgi?id=672)
  73   long story, pospopcount needs bmatflip (aka vgbbd in VSX)
  74   but also needed sv.bc fixing
  75   [bug #1215](https://bugs.libre-soc.org/show_bug.cgi?id=1215)
  76   which is related/similar to the DDFFirst issue on scalar source/dest
  77   [bug #1183](https://bugs.libre-soc.org/show_bug.cgi?id=1183)
  78   which jacob also noted for sv.cmpi/ff needed on bigmul.
  79 * Guide Dmitry on svanalysis.py.
  80 * Guide Shriya in Poly1305
  81   [bug #1157](https://bugs.libre-soc.org/show_bug.cgi?id=1157)
  82   and ED25519 [bug #1151](https://bugs.libre-soc.org/show_bug.cgi?id=1151)
  83   to assist Sadoon.
  84
  85 # Shriya
  86
  87 - Work together with Sadoon on Poly1305 and ED25519.
  88
  89 # Tobias
  90
  91 * created fosdem talk bug, [bug #1213](https://bugs.libre-soc.org/show_bug.cgi?id=1213)
  92
  93 [[!tag meeting2023]]
  94 [[!tag meeting_sync_up]]
  95