1 { version, litexPkgs }:
3 { stdenv, python3Packages, yosys, libresoc-verilog }:
9 src = ../src/soc/litex/florent;
13 nativeBuildInputs = (with python3Packages; [
14 python migen c4m-jtag nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa
15 ]) ++ (with litexPkgs; [ litex litedram liteeth liteiclink litescope litesdcard ]);
18 patchShebangs --build .
20 export PYTHONPATH="${../src}:$PYTHONPATH"
23 configurePhase = "true";
27 cp ${libresoc-verilog} libresoc/libresoc.v
28 ./ls180soc.py --build --platform=ls180sram4k --num-srams=2 --srams4k
35 mv build/ls180sram4k/gateware/ls180sram4k.v $out/ls180.v
36 mv build/ls180sram4k/gateware/mem.init $out
37 mv build/ls180sram4k/gateware/mem_1.init $out
38 mv libresoc/libresoc.v $out
39 mv libresoc/SPBlock_512W64B8W.v $out