3 { stdenv, python3Packages }:
13 nativeBuildInputs = with python3Packages; [
14 c4m-jtag nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa
17 configurePhase = "true";
22 export PYTHONPATH="$PWD:$PYTHONPATH"
23 python3 soc/simple/issuer_verilog.py \
24 --debug=jtag --enable-core --enable-pll \
25 --enable-xics --enable-sram4x4kblock --disable-svp64 \