nlnet_2019_coriolis2.mdwn

   1 # NLnet.net LIP6.fr Coriolis2 proposal
   2
   3 * [[questions]]
   4 * approved 20dec2019
   5 * MOU TBD
   6 * NLNet Project Page <https://nlnet.nl/project/Coriolis2/>
   7
   8 ## Project name
   9
  10 The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration
  11
  12 ## Website / wiki
  13
  14 <https://libre-riscv.org/nlnet_2019_coriolis2>
  15
  16 Please be short and to the point in your answers; focus primarily on
  17 the what and how, not so much on the why. Add longer descriptions as
  18 attachments (see below). If English isn't your first language, don't
  19 worry - our reviewers don't care about spelling errors, only about
  20 great ideas. We apologise for the inconvenience of having to submit in
  21 English. On the up side, you can be as technical as you need to be (but
  22 you don't have to). Do stay concrete. Use plain text in your reply only,
  23 if you need any HTML to make your point please include this as attachment.
  24
  25 ## Abstract: Can you explain the whole project and its expected outcome(s).
  26
  27 The Libre RISC-V SoC is being developed to provide a privacy-respecting
  28 modern processor, developed transparently and as libre to the bedrock
  29 as possible.  This means not just the software running on the processor:
  30 it means the actual hardware design and the hardware layout, right down
  31 to the transistor level.
  32
  33 It is necessary, therefore, to use libre-licensed VLSI Layout tools
  34 rather than pay for proprietary software that, apart from being incredibly
  35 expensive, could potentially compromise the integrity of the project.
  36
  37 We therefore intend to collaborate with engineers from LIP6, to use
  38 and improve their VLSI Layout tool, Coriolis2, in conjunction with
  39 Chips4Makers, to create the layout that Chips4Makers will then put into
  40 a 180nm 300mhz test chip.
  41
  42 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  43
  44 Luke Leighton is an ethical technology specialist who has a consistent
  45 24-year track record of developing code in a real-time transparent
  46 (fully libre) fashion, and in managing Software Libre teams.  He is the
  47 lead developer on the Libre RISC-V SoC.
  48
  49 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
  50 tools for VLSI backend layout, from LIP6.
  51
  52 # Requested Amount
  53
  54 EUR 50,000.
  55
  56 # Explain what the requested budget will be used for?
  57
  58 The key initial milestone for the 2018 NLNet Libre RISC-V SoC Project
  59 is the FPGA target: a working design that can run in an FPGA at approximately
  60 50Mhz.  The next logical step is to do the layout.
  61
  62 However, FPGA targets have some quirks which help accelerate FPGAs (not ASICs):
  63 an on-board DSP, specialist memory, and so on.  Without these "crutches"
  64 the design must be augmented and adapted to suit ASIC layout.
  65
  66 As we are using nmigen for the HDL front-end and yosys for the HDL
  67 back-end, we will need to work with the nmigen developers in order to
  68 augment nmigen to cope with the task of creating "netlists" suitable for
  69 ASICs.  Whilst yosys (the actual "netlist" generator) has been utilised
  70 for this task repeatedly and successfully, and whilst the prior version,
  71 "migen", was also used, nmigen has not yet been ASIC proven.
  72
  73 Once a "netlist" is available, the Coriolis2 VLSI tool will be used to
  74 actually create the layers of the chip.  Given the size and capabilities
  75 of the chip, we anticipate issues here, which we will need the support
  76 of LIP6's engineers to solve.
  77
  78 The layout itself is also dependent on what is called "Cell Libraries".
  79 One is "NSXLIB" which contains OR and AND gates to create MUXes and XORs.
  80 Another is an "SRAM" Library (memory), and another is a "GPIO" Cell
  81 Library.  Chips4Makers will be working on these low-level blocks for
  82 us (under a separate Programme), however we again anticipate issues -
  83 related to Foundry NDAs - which will hamper the communications process.
  84
  85 So therefore, the requested budget will be used for:
  86
  87 * Augmentation and adaptation of the Libre RISC-V SoC HDL to ASIC layout
  88 * Engineers to work on the layout using Alliance / Coriolos2 VLSI, from lip6
  89 * Engineers to bug-fix or augment Alliance / Coriolis2
  90 * Essential augmentations to nmigen to make it ASIC-layout-capable
  91
  92 All of these will be and are entirely libre-licensed software: there will
  93 be no proprietary software tools utilised in this process.
  94
  95
  96 # Does the project have other funding sources, both past and present?
  97
  98 The overall project has sponsorship from Purism as well as a prior grant
  99 from NLNet.  However that is for specifically covering the development
 100 of the RTL (the hardware source code).
 101
 102 There is no source of funds for the work on the *next* stage: the actual
 103 VLSI ASIC Layout.  Chips4Makers is however putting in an *additional*
 104 (and separate) funding application for the stage after *this*: the
 105 creation of the Cell Libraries that will be used in the VLSI ASIC Layout.
 106
 107 All these three projects are separate and distinct (despite being related
 108 to the same CPU), and funding may not cross over from one project to
 109 the other.
 110
 111 # Compare your own project with existing or historical efforts.
 112
 113 There are several Open VLSI Tool suites:
 114
 115 * GNU Electric: https://www.gnu.org/software/electric/
 116 * MAGIC: http://opencircuitdesign.com/magic/
 117 * The OpenROAD Project: https://theopenroadproject.org/ (using MAGIC)
 118 * QFlow: http://opencircuitdesign.com/qflow/
 119 * Toped: http://www.toped.org.uk/
 120
 121 and a few more.  We choose Coriolis2 because of its python interface.
 122 The VLSI Layout is actually done as a *python* program.  With nmigen
 123 (the HDL) being in python, we anticipate the same OO benefits to be
 124 achievable in coriolis2 as well.
 125
 126 The case for the Libre RISC-V SoC itself was made already in the initial
 127 2018.02 proposal.  That has not changed: there are no Libre / Open Projects
 128 approaching anything like the complexity and product market opportunities
 129 of the Libre RISC-V SoC, which is being designed to be a quad-core 800mhz
 130 multi-issue out-of-order design.  All other Libre / Open processors such
 131 as Raven, and many more, have a goal set in advance not to exceed around
 132 the 350mhz mark, and are single-core.
 133
 134 Other projects which are "open", such as the Ariane Processor, are
 135 developed by universities, and in the case of Ariane were *SPECIFICALLY*
 136 designed by and for the use of proprietary toolchains, such as those from
 137 Cadence, Synopsys and Mentor Graphics.  Despite the source code being
 138 "open", there was absolutely no expectation that the processor of the
 139 same capability as the Libre RISC-V SoC would use Libre / Open tools.
 140
 141 Although our first ASIC (thanks to Chips4Makers) will be only 180nm,
 142 single-core and a maximum of around 350mhz, this is just the first
 143 stepping stone to a much larger processor.
 144
 145 ## What are significant technical challenges you expect to solve during the project, if any?
 146
 147 Some of these have been mentioned above:
 148
 149 * NDAs by Foundries may interfere with the ability for Chips4Makers to
 150   communicate with LIP6 regarding the necessary changes to NSXLIB which
 151   meet the TSMC Foundry "Design Rule Checks" (DRCs).
 152 * Bugs or missing features in nmigen, yosys, coriolis2, NSXLIB, OpenRAM,
 153   and the knock-on implications throughout the chain, right the way up
 154   to the *actual* Libre RISC-V SoC's HDL source code itself, all need to
 155   be dealt with.
 156 * Circuit simulation and unit testing is going to be a major factor, and
 157   a huge utilisation of Computing power.  Machines with "only" 16 GB of RAM
 158   and high-end quad-core processors are going to be hopelessly inadequate.
 159
 160 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 161
 162 LIP6 have their own mailing list for the (transparent) discussion of
 163 issues related to coriolis2: <alliance-users@asim.lip6.fr>.  The Libre RISC-V
 164 SoC has a full set of resources for Libre Project Management and development:
 165 mailing list, bugtracker, git repository and wiki - all listed here:
 166 <https://libre-riscv.org/>
 167
 168 In addition, we have a Crowdsupply page
 169 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 170 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 171 all picked up the story.  The list is updated and maintained here:
 172 <https://libre-riscv.org/3d_gpu/>
 173
 174 # Extra info to be submitted
 175
 176 * <http://libre-riscv.org/3d_gpu/>
 177 * <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
 178 * <https://nlnet.nl/project/Libre-RISCV/>
 179 * <https://chips4makers.io/blog/>
 180