nlnet_2019_coriolis2.mdwn

   1 # NL.net proposal
   2
   3 ## Project name
   4
   5 The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration
   6
   7 ## Website / wiki
   8
   9 <https://libre-riscv.org/nlnet_2019_coriolis2>
  10
  11 Please be short and to the point in your answers; focus primarily on
  12 the what and how, not so much on the why. Add longer descriptions as
  13 attachments (see below). If English isn't your first language, don't
  14 worry - our reviewers don't care about spelling errors, only about
  15 great ideas. We apologise for the inconvenience of having to submit in
  16 English. On the up side, you can be as technical as you need to be (but
  17 you don't have to). Do stay concrete. Use plain text in your reply only,
  18 if you need any HTML to make your point please include this as attachment.
  19
  20 ## Abstract: Can you explain the whole project and its expected outcome(s).
  21
  22 The Libre RISC-V SoC is being developed to provide a privacy-respecting
  23 modern processor, developed transparently and as libre to the bedrock
  24 as possible.  This means not just the software running on the processor:
  25 it means the actual hardware design and the hardware layout, right down
  26 to the transistor level.
  27
  28 It is necessary, therefore, to use libre-licensed VLSI Layout tools
  29 rather than pay for proprietary software that, apart from being incredibly
  30 expensive, could potentially compromise the integrity of the project.
  31
  32 We therefore intend to collaborate with engineers from the Laboratoire
  33 d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
  34 Coriolis2, in conjunction with Chips4Makers, to create the layout that
  35 Chips4Makers will then put into a 180nm 300mhz test chip.
  36
  37 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  38
  39 Luke Leighton is an ethical technology specialist who has a consistent
  40 24-year track record of developing code in a real-time transparent
  41 (fully libre) fashion, and in managing Software Libre teams.  He is the
  42 lead developer on the Libre RISC-V SoC.
  43
  44 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
  45 tools for VLSI backend layout, from the Laboratoire d'Informatique de
  46 Paris 6.
  47
  48 # Requested Amount
  49
  50 EUR $50,000.
  51
  52 # Explain what the requested budget will be used for?
  53
  54 The key initial milestone for the 2018 NLNet Libre RISC-V SoC Project
  55 is the FPGA target: a working design that can run in an FPGA at approximately
  56 50Mhz.  The next logical step is to do the layout.
  57
  58 However, FPGA targets have some quirks which help accelerate FPGAs (not ASICs):
  59 an on-board DSP, specialist memory, and so on.  Without these "crutches"
  60 the design must be augmented and adapted to suit ASIC layout.
  61
  62 As we are using nmigen for the HDL front-end and yosys for the HDL
  63 back-end, we will need to work with the nmigen developers in order to
  64 augment nmigen to cope with the task of creating "netlists" suitable for
  65 ASICs.  Whilst yosys (the actual "netlist" generator) has been utilised
  66 for this task repeatedly and successfully, and whilst the prior version,
  67 "migen", was also used, nmigen has not yet been ASIC proven.
  68
  69 Once a "netlist" is available, the Coriolis2 VLSI tool will be used to
  70 actually create the layers of the chip.  Given the size and capabilities
  71 of the chip, we anticipate issues here, which we will need the support
  72 of LIP6's engineers to solve.
  73
  74 The layout itself is also dependent on what is called "Cell Libraries".
  75 One is "NSXLIB" which contains OR and AND gates to create MUXes and XORs.
  76 Another is an "SRAM" Library (memory), and another is a "GPIO" Cell
  77 Library.  Chips4Makers will be working on these low-level blocks for
  78 us (under a separate Programme), however we again anticipate issues -
  79 related to Foundry NDAs - which will hamper the communications process.
  80
  81 So therefore, the requested budget will be used for:
  82
  83 * Augmentation and adaptation of the Libre RISC-V SoC HDL to ASIC layout
  84 * Engineers to work on the layout using Alliance / Coriolos2 VLSI, from lip6
  85 * Engineers to bug-fix or augment Alliance / Coriolis2
  86 * Essential augmentations to nmigen to make it ASIC-layout-capable
  87
  88 All of these will be and are entirely libre-licensed software: there will
  89 be no proprietary software tools utilised in this process.  Note that
  90
  91
  92 # Does the project have other funding sources, both past and present?
  93
  94
  95 # Compare your own project with existing or historical efforts.
  96
  97
  98 ## What are significant technical challenges you expect to solve during the project, if any?
  99
 100
 101 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 102
 103 We have a pre-launch Crowdsupply page up and running already, at
 104 https://www.crowdsupply.com/libre-risc-v/m-class through which we will
 105 engage with developers and end-users alike.  Developers will be invited
 106 to participate through the http://libre-riscv.org website and resources.
 107
 108 The Crowdsupply page has already been picked up by Phoronix, Heise.de
 109 Magazine, reddit and ycombinator.  There is a lot of interest in this
 110 project.
 111
 112 # Extra info to be submitted
 113
 114 * <https://hardware.slashdot.org/story/18/12/11/1410200/super-micro-says-review-found-no-malicious-chips-in-motherboards>
 115 * <https://libreboot.org/faq.html#intelme>