nlnet_2019_coriolis2.mdwn

   1 # NLnet.net LIP6.fr Coriolis2 proposal
   2
   3 * [[questions]]
   4 * approved 20dec2019
   5 * MOU TBD
   6
   7 ## Project name
   8
   9 The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration
  10
  11 ## Website / wiki
  12
  13 <https://libre-riscv.org/nlnet_2019_coriolis2>
  14
  15 Please be short and to the point in your answers; focus primarily on
  16 the what and how, not so much on the why. Add longer descriptions as
  17 attachments (see below). If English isn't your first language, don't
  18 worry - our reviewers don't care about spelling errors, only about
  19 great ideas. We apologise for the inconvenience of having to submit in
  20 English. On the up side, you can be as technical as you need to be (but
  21 you don't have to). Do stay concrete. Use plain text in your reply only,
  22 if you need any HTML to make your point please include this as attachment.
  23
  24 ## Abstract: Can you explain the whole project and its expected outcome(s).
  25
  26 The Libre RISC-V SoC is being developed to provide a privacy-respecting
  27 modern processor, developed transparently and as libre to the bedrock
  28 as possible.  This means not just the software running on the processor:
  29 it means the actual hardware design and the hardware layout, right down
  30 to the transistor level.
  31
  32 It is necessary, therefore, to use libre-licensed VLSI Layout tools
  33 rather than pay for proprietary software that, apart from being incredibly
  34 expensive, could potentially compromise the integrity of the project.
  35
  36 We therefore intend to collaborate with engineers from LIP6, to use
  37 and improve their VLSI Layout tool, Coriolis2, in conjunction with
  38 Chips4Makers, to create the layout that Chips4Makers will then put into
  39 a 180nm 300mhz test chip.
  40
  41 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  42
  43 Luke Leighton is an ethical technology specialist who has a consistent
  44 24-year track record of developing code in a real-time transparent
  45 (fully libre) fashion, and in managing Software Libre teams.  He is the
  46 lead developer on the Libre RISC-V SoC.
  47
  48 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
  49 tools for VLSI backend layout, from LIP6.
  50
  51 # Requested Amount
  52
  53 EUR 50,000.
  54
  55 # Explain what the requested budget will be used for?
  56
  57 The key initial milestone for the 2018 NLNet Libre RISC-V SoC Project
  58 is the FPGA target: a working design that can run in an FPGA at approximately
  59 50Mhz.  The next logical step is to do the layout.
  60
  61 However, FPGA targets have some quirks which help accelerate FPGAs (not ASICs):
  62 an on-board DSP, specialist memory, and so on.  Without these "crutches"
  63 the design must be augmented and adapted to suit ASIC layout.
  64
  65 As we are using nmigen for the HDL front-end and yosys for the HDL
  66 back-end, we will need to work with the nmigen developers in order to
  67 augment nmigen to cope with the task of creating "netlists" suitable for
  68 ASICs.  Whilst yosys (the actual "netlist" generator) has been utilised
  69 for this task repeatedly and successfully, and whilst the prior version,
  70 "migen", was also used, nmigen has not yet been ASIC proven.
  71
  72 Once a "netlist" is available, the Coriolis2 VLSI tool will be used to
  73 actually create the layers of the chip.  Given the size and capabilities
  74 of the chip, we anticipate issues here, which we will need the support
  75 of LIP6's engineers to solve.
  76
  77 The layout itself is also dependent on what is called "Cell Libraries".
  78 One is "NSXLIB" which contains OR and AND gates to create MUXes and XORs.
  79 Another is an "SRAM" Library (memory), and another is a "GPIO" Cell
  80 Library.  Chips4Makers will be working on these low-level blocks for
  81 us (under a separate Programme), however we again anticipate issues -
  82 related to Foundry NDAs - which will hamper the communications process.
  83
  84 So therefore, the requested budget will be used for:
  85
  86 * Augmentation and adaptation of the Libre RISC-V SoC HDL to ASIC layout
  87 * Engineers to work on the layout using Alliance / Coriolos2 VLSI, from lip6
  88 * Engineers to bug-fix or augment Alliance / Coriolis2
  89 * Essential augmentations to nmigen to make it ASIC-layout-capable
  90
  91 All of these will be and are entirely libre-licensed software: there will
  92 be no proprietary software tools utilised in this process.
  93
  94
  95 # Does the project have other funding sources, both past and present?
  96
  97 The overall project has sponsorship from Purism as well as a prior grant
  98 from NLNet.  However that is for specifically covering the development
  99 of the RTL (the hardware source code).
 100
 101 There is no source of funds for the work on the *next* stage: the actual
 102 VLSI ASIC Layout.  Chips4Makers is however putting in an *additional*
 103 (and separate) funding application for the stage after *this*: the
 104 creation of the Cell Libraries that will be used in the VLSI ASIC Layout.
 105
 106 All these three projects are separate and distinct (despite being related
 107 to the same CPU), and funding may not cross over from one project to
 108 the other.
 109
 110 # Compare your own project with existing or historical efforts.
 111
 112 There are several Open VLSI Tool suites:
 113
 114 * GNU Electric: https://www.gnu.org/software/electric/
 115 * MAGIC: http://opencircuitdesign.com/magic/
 116 * The OpenROAD Project: https://theopenroadproject.org/ (using MAGIC)
 117 * QFlow: http://opencircuitdesign.com/qflow/
 118 * Toped: http://www.toped.org.uk/
 119
 120 and a few more.  We choose Coriolis2 because of its python interface.
 121 The VLSI Layout is actually done as a *python* program.  With nmigen
 122 (the HDL) being in python, we anticipate the same OO benefits to be
 123 achievable in coriolis2 as well.
 124
 125 The case for the Libre RISC-V SoC itself was made already in the initial
 126 2018.02 proposal.  That has not changed: there are no Libre / Open Projects
 127 approaching anything like the complexity and product market opportunities
 128 of the Libre RISC-V SoC, which is being designed to be a quad-core 800mhz
 129 multi-issue out-of-order design.  All other Libre / Open processors such
 130 as Raven, and many more, have a goal set in advance not to exceed around
 131 the 350mhz mark, and are single-core.
 132
 133 Other projects which are "open", such as the Ariane Processor, are
 134 developed by universities, and in the case of Ariane were *SPECIFICALLY*
 135 designed by and for the use of proprietary toolchains, such as those from
 136 Cadence, Synopsys and Mentor Graphics.  Despite the source code being
 137 "open", there was absolutely no expectation that the processor of the
 138 same capability as the Libre RISC-V SoC would use Libre / Open tools.
 139
 140 Although our first ASIC (thanks to Chips4Makers) will be only 180nm,
 141 single-core and a maximum of around 350mhz, this is just the first
 142 stepping stone to a much larger processor.
 143
 144 ## What are significant technical challenges you expect to solve during the project, if any?
 145
 146 Some of these have been mentioned above:
 147
 148 * NDAs by Foundries may interfere with the ability for Chips4Makers to
 149   communicate with LIP6 regarding the necessary changes to NSXLIB which
 150   meet the TSMC Foundry "Design Rule Checks" (DRCs).
 151 * Bugs or missing features in nmigen, yosys, coriolis2, NSXLIB, OpenRAM,
 152   and the knock-on implications throughout the chain, right the way up
 153   to the *actual* Libre RISC-V SoC's HDL source code itself, all need to
 154   be dealt with.
 155 * Circuit simulation and unit testing is going to be a major factor, and
 156   a huge utilisation of Computing power.  Machines with "only" 16 GB of RAM
 157   and high-end quad-core processors are going to be hopelessly inadequate.
 158
 159 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 160
 161 LIP6 have their own mailing list for the (transparent) discussion of
 162 issues related to coriolis2: <alliance-users@asim.lip6.fr>.  The Libre RISC-V
 163 SoC has a full set of resources for Libre Project Management and development:
 164 mailing list, bugtracker, git repository and wiki - all listed here:
 165 <https://libre-riscv.org/>
 166
 167 In addition, we have a Crowdsupply page
 168 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 169 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 170 all picked up the story.  The list is updated and maintained here:
 171 <https://libre-riscv.org/3d_gpu/>
 172
 173 # Extra info to be submitted
 174
 175 * <http://libre-riscv.org/3d_gpu/>
 176 * <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
 177 * <https://nlnet.nl/project/Libre-RISCV/>
 178 * <https://chips4makers.io/blog/>
 179