nlnet_2019_coriolis2.mdwn

   1 # NL.net proposal
   2
   3 ## Project name
   4
   5 The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration
   6
   7 ## Website / wiki
   8
   9 <https://libre-riscv.org/nlnet_2019_coriolis2>
  10
  11 Please be short and to the point in your answers; focus primarily on
  12 the what and how, not so much on the why. Add longer descriptions as
  13 attachments (see below). If English isn't your first language, don't
  14 worry - our reviewers don't care about spelling errors, only about
  15 great ideas. We apologise for the inconvenience of having to submit in
  16 English. On the up side, you can be as technical as you need to be (but
  17 you don't have to). Do stay concrete. Use plain text in your reply only,
  18 if you need any HTML to make your point please include this as attachment.
  19
  20 ## Abstract: Can you explain the whole project and its expected outcome(s).
  21
  22 The Libre RISC-V SoC is being developed to provide a privacy-respecting
  23 modern processor, developed transparently and as libre to the bedrock
  24 as possible.  This means not just the software running on the processor:
  25 it means the actual hardware design and the hardware layout, right down
  26 to the transistor level.
  27
  28 It is necessary, therefore, to use libre-licensed VLSI Layout tools
  29 rather than pay for proprietary software that, apart from being incredibly
  30 expensive, could potentially compromise the integrity of the project.
  31
  32 We therefore intend to collaborate with engineers from the Laboratoire
  33 d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
  34 Coriolis2, in conjunction with Chips4Makers, to create the layout that
  35 Chips4Makers will then put into a 180nm 300mhz test chip.
  36
  37 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  38
  39 Luke Leighton is an ethical technology specialist who has a consistent
  40 24-year track record of developing code in a real-time transparent
  41 (fully libre) fashion, and in managing Software Libre teams.  He is the
  42 lead developer on the Libre RISC-V SoC.
  43
  44 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
  45 tools for VLSI backend layout, from the Laboratoire d'Informatique de
  46 Paris 6.
  47
  48 # Requested Amount
  49
  50 EUR 50,000.
  51
  52 # Explain what the requested budget will be used for?
  53
  54 The key initial milestone for the 2018 NLNet Libre RISC-V SoC Project
  55 is the FPGA target: a working design that can run in an FPGA at approximately
  56 50Mhz.  The next logical step is to do the layout.
  57
  58 However, FPGA targets have some quirks which help accelerate FPGAs (not ASICs):
  59 an on-board DSP, specialist memory, and so on.  Without these "crutches"
  60 the design must be augmented and adapted to suit ASIC layout.
  61
  62 As we are using nmigen for the HDL front-end and yosys for the HDL
  63 back-end, we will need to work with the nmigen developers in order to
  64 augment nmigen to cope with the task of creating "netlists" suitable for
  65 ASICs.  Whilst yosys (the actual "netlist" generator) has been utilised
  66 for this task repeatedly and successfully, and whilst the prior version,
  67 "migen", was also used, nmigen has not yet been ASIC proven.
  68
  69 Once a "netlist" is available, the Coriolis2 VLSI tool will be used to
  70 actually create the layers of the chip.  Given the size and capabilities
  71 of the chip, we anticipate issues here, which we will need the support
  72 of LIP6's engineers to solve.
  73
  74 The layout itself is also dependent on what is called "Cell Libraries".
  75 One is "NSXLIB" which contains OR and AND gates to create MUXes and XORs.
  76 Another is an "SRAM" Library (memory), and another is a "GPIO" Cell
  77 Library.  Chips4Makers will be working on these low-level blocks for
  78 us (under a separate Programme), however we again anticipate issues -
  79 related to Foundry NDAs - which will hamper the communications process.
  80
  81 So therefore, the requested budget will be used for:
  82
  83 * Augmentation and adaptation of the Libre RISC-V SoC HDL to ASIC layout
  84 * Engineers to work on the layout using Alliance / Coriolos2 VLSI, from lip6
  85 * Engineers to bug-fix or augment Alliance / Coriolis2
  86 * Essential augmentations to nmigen to make it ASIC-layout-capable
  87
  88 All of these will be and are entirely libre-licensed software: there will
  89 be no proprietary software tools utilised in this process.  Note that
  90
  91
  92 # Does the project have other funding sources, both past and present?
  93
  94 The overall project has sponsorship from Purism as well as a prior grant
  95 from NLNet.  However that is for specifically covering the development
  96 of the RTL (the hardware source code).
  97
  98 There is no source of funds for the work on the *next* stage: the actual
  99 VLSI ASIC Layout.  Chips4Makers is however putting in an *additional*
 100 (and separate) funding application for the stage after *this*: the
 101 creation of the Cell Libraries that will be used in the VLSI ASIC Layout.
 102
 103 All these three projects are separate and distinct (despite being related
 104 to the same CPU), and funding may not cross over from one project to
 105 the other.
 106
 107 # Compare your own project with existing or historical efforts.
 108
 109 There are several Open VLSI Tool suites:
 110
 111 * GNU Electric: https://www.gnu.org/software/electric/
 112 * MAGIC: http://opencircuitdesign.com/magic/
 113 * The OpenROAD Project: https://theopenroadproject.org/ (using MAGIC)
 114 * QFlow: http://opencircuitdesign.com/qflow/
 115 * Toped: http://www.toped.org.uk/
 116
 117 and a few more.  We choose Coriolis2 because of its python interface.
 118 The VLSI Layout is actually done as a *python* program.  With nmigen
 119 (the HDL) being in python, we anticipate the same OO benefits to be
 120 achievable in coriolis2 as well.
 121
 122 The case for the Libre RISC-V SoC itself was made already in the initial
 123 2018.02 proposal.  That has not changed: there are no Libre / Open Projects
 124 approaching anything like the complexity and product market opportunities
 125 of the Libre RISC-V SoC, which is being designed to be a quad-core 800mhz
 126 multi-issue out-of-order design.  All other Libre / Open processors such
 127 as Raven, and many more, have a goal set in advance not to exceed around
 128 the 350mhz mark, and are single-core.
 129
 130 Other projects which are "open", such as the Ariane Processor, are
 131 developed by universities, and in the case of Ariane were *SPECIFICALLY*
 132 designed by and for the use of proprietary toolchains, such as those from
 133 Cadence, Synopsys and Mentor Graphics.  Despite the source code being
 134 "open", there was absolutely no expectation that the processor of the
 135 same capability as the Libre RISC-V SoC would use Libre / Open tools.
 136
 137 Although our first ASIC (thanks to Chips4Makers) will be only 180nm,
 138 single-core and a maximum of around 350mhz, this is just the first
 139 stepping stone to a much larger processor.
 140
 141 ## What are significant technical challenges you expect to solve during the project, if any?
 142
 143 Some of these have been mentioned above:
 144
 145 * NDAs by Foundries may interfere with the ability for Chips4Makers to
 146   communicate with LIP6 regarding the necessary changes to NSXLIB which
 147   meet the TSMC Foundry "Design Rule Checks" (DRCs).
 148 * Bugs or missing features in nmigen, yosys, coriolis2, NSXLIB, OpenRAM,
 149   and the knock-on implications throughout the chain, right the way up
 150   to the *actual* Libre RISC-V SoC's HDL source code itself, all need to
 151   be dealt with.
 152 * Circuit simulation and unit testing is going to be a major factor, and
 153   a huge utilisation of Computing power.  Machines with "only" 16 GB of RAM
 154   and high-end quad-core processors are going to be hopelessly inadequate.
 155
 156 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 157
 158 LIP6 have their own mailing list for the (transparent) discussion of
 159 issues related to coriolis2: <alliance-users@asim.lip6.fr>.  The Libre RISC-V
 160 SoC has a full set of resources for Libre Project Management and development:
 161 mailing list, bugtracker, git repository and wiki - all listed here:
 162 <https://libre-riscv.org/>
 163
 164 In addition, we have a Crowdsupply page
 165 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 166 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 167 all picked up the story.  The list is updated and maintained here:
 168 <https://libre-riscv.org/3d_gpu/>
 169
 170 # Extra info to be submitted
 171
 172 * <http://libre-riscv.org/3d_gpu/>
 173 * <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
 174 * <https://nlnet.nl/project/Libre-RISCV/>
 175 * <https://chips4makers.io/blog/>
 176